Low-Threshold-Voltage MoN/HfAlO/SiON p-MOSFETs With 0.85-nm EOT

doi:10.1109/LED.2009.2023824

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chang, M. F.	en_US
dc.contributor.author	Lee, P. T.	en_US
dc.contributor.author	Chin, Albert	en_US
dc.date.accessioned	2014-12-08T15:09:02Z	-
dc.date.available	2014-12-08T15:09:02Z	-
dc.date.issued	2009-08-01	en_US
dc.identifier.issn	0741-3106	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/LED.2009.2023824	en_US
dc.identifier.uri	http://hdl.handle.net/11536/6873	-
dc.description.abstract	By using HfAlO as a capping layer on SiON, MoN/HfAlO/SiON p-MOSFETs show an effective work function of 5.1 eV, a low threshold voltage of -0.1 V, and a peak hole mobility of 80 cm(2)/(V . s) at small equivalent oxide thickness of 0.85 nm. These self-aligned and gate-first p-MOSFETs processes, with standard ion implantation and 1000 degrees C rapid thermal annealing, are fully compatible with current very large scale integration fabrication lines.	en_US
dc.language.iso	en_US	en_US
dc.subject	Capping layer	en_US
dc.subject	HfAlO	en_US
dc.subject	MoN	en_US
dc.subject	p-MOSFETs	en_US
dc.title	Low-Threshold-Voltage MoN/HfAlO/SiON p-MOSFETs With 0.85-nm EOT	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/LED.2009.2023824	en_US
dc.identifier.journal	IEEE ELECTRON DEVICE LETTERS	en_US
dc.citation.volume	30	en_US
dc.citation.issue	8	en_US
dc.citation.spage	861	en_US
dc.citation.epage	863	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	光電工程學系	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.contributor.department	Department of Photonics	en_US
dc.identifier.wosnumber	WOS:000268342400024	-
dc.citation.woscount	7	-
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