鎖相迴路障礙診斷之可測試性電路設計

Abstract

本論文是針對鎖相迴做障礙診斷的可測試性電路設計。在現今的通訊領域當中，鎖相迴路扮演相當重要的角色，像是低抖動的頻率合成器、時脈回復和同步作用；當鎖相迴路中有障礙存在時，所提供的頻率和效能將會與規格不符。因此，在量產測試不符合規格時，若能診斷出錯誤的部分，將能夠縮短除錯時間、縮小除錯範圍，進而提升良率、降低生產成本。 本文中，我們提出了一個診斷鎖相迴路可測試性電路設計的方法，在鎖相迴路當中增加了兩個測試時脈和隨測試時脈而變動的一些測試電路，診斷出在鎖相迴路當中一些具代表性的障礙，並對壓控震盪器的障礙作分析。最後我們用tsmc 0.35 CMOS製成完成全部得電路並證明這個診斷方法的可行性。

This thesis proposes a DFT scheme for phase-locked loop diagnosis. PLL plays a very import role in communication systems nowadays, such as low-jitter PLL-based frequency synthesizer、clock recovery and synchronization. For the PLL, to improve the yield and achieve cost reduction, it is important to diagnose it to identify the faulty part when it does not meet the specifications as expected. In the thesis, a DFT scheme for PLL diagnosis is presented. Two test clocks and design-for-test(DFT) circuits controlled by test clocks are applied. The proposed method identifies some representative faults and analyzes faults in VCO. Ultimately, we completed the whole circuit with 0.35-μm N-well technology as an example to demonstrate the feasibility.