標題: 限定輸出誤差之乘法器自動合成
On Multiplier Synthesis under Error Constraint
作者: 林昭斌
Chaobin Lin
周景揚
Jing-Yang Jou
電子研究所
關鍵字: 乘法;乘法器;multiplication;multiplier
公開日期: 2001
摘要: 在各種處理器中,乘法器的速度往往是決定效能的關鍵。再者,由於在各種電路中廣泛的使用乘法器,因此如何自動化的產生需要的乘法器,成為電路設計自動化的重要課題。在本篇論文中,我們提出了由誤差大小來決定硬體的自動乘法產生器。藉著容許些許的誤差,我們可以用更小的面積來實現更快速的乘法器。考慮到信號到達時間的曲線圖,我們也為以時間為考量的繞線和電路配置(placement)提出一些技巧,來做時序最佳化。在乘法產生器的流程中,藉由整合電路合成、配置以及再合成的步驟,我們將可得到優於其他傳統作法產生的乘法器。
The thesis presents an automatic error-controlled hardware-configurable multiplier generator. The determination of the hardware of a multiplier is based on the error constraint given by users. With allowing some rounding errors, a significant reduction in area and delay can be achieved. By considering signal arrival profile, we also proposed several techniques for timing driven routing and placement to optimize the timing. By integrating synthesis, placement and resynthesis processes in the multiplier generation flow, the multipliers generated by our multiplier generator outperform other schemes used for comparison as shown in our experimental results.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT900428088
http://hdl.handle.net/11536/68777
Appears in Collections:Thesis