適用於多種影像壓縮標準的高產出率及低功率算數編解碼器設計

Abstract

算數編碼在過去幾年來有越來越被重視的趨勢。許多未來的國際標準都把算數編碼列為關鍵元件。因此，其相關的硬體研究也就越顯重要。在本論文中，我們提出了一個硬體架構同時適用在JPEG, JBIG, JPEG-2000及JBIG2所使用的MQ及QM編碼器。他成功的將架構管線化為三個階段並達到每個週期能夠編碼或解碼出一個符號的效率。在低功率的考量上，使用了硬體共享及動態關閉時脈的機制。我們同時提出了使用動態關閉時脈技術的系統化設計流程，從硬體描述語言的指導原則到合成與佈局時的時脈樹產生技術。使用我們的架構，JPEG-2000的算數編解碼器的編碼及解碼產出率將可以分別達到200Msymbol/sec及182Msymbol/sec。其邏輯閘數僅有10K且在100Mhz下也僅消耗低於20mA的電流。至於支援多標準的編解碼器，其編碼及解碼的產出率分別為133Msymbol/sec及125Msymbol/sec。其邏輯閘數約為14K。因此，我們的設計擁有符合多標準，高產出率，低功率，低成本的特性，能夠付合即時及可攜性應用上的需求。

Arithmetic coding has become more and more popular in recent years. Many future international standard adopt arithmetic coding as its essential element. Its related hardware architecture research is in great demand. In this thesis, we proposed an architecture support both MQ and QM coder that adopt in JPEG, JBIG, JPEG-2000 and JBIG2. It successfully pipelines the design into three stages that can encode and decode a symbol in each cycle. For low power consideration, hardware sharing and dynamic gated clock mechanism is exploited in our design. We also proposed a systematic way to exploit dynamic gated clock mechanism into a system from RTL coding guideline, synthesis constraint to APR clock tree generation. Using our proposed architecture, encoding and decoding throughput rate of arithmetic codec for JPEG-2000 is up to 200Msymbol/sec and 182Msymbol/sec respectively while only cost 10K gate count and consume less than 20mA@100Mhz. As for multi-standard codec, encode and decode throughput rate runs up to 133Msymbol/sec and 125Msymbol/sec respectively. It costs 14K gate count. As a result, our design adopted multi-standard, high-throughput, low power and low cost characteristic that can be used for real-time and portable applications.