用於正交分頻多工通信系統之快速傅立業轉換處理器之研究設計

Abstract

本論文針對幾種傅立葉演算法去分析比較其算術複雜度，並對不同的架構做硬體效率、硬體成本和速度上的比較分析。最後整合提出一個適用於各種正交分頻多工調變系統的快速傅立業處理器架構，即可變長度單一處理單元架構。其可提供足夠的效能並且可用於所有2n點數的快速傅立業轉換。除此之外，我們亦介紹使用幾種設計技巧可用來簡化硬體複雜度，如：位元長度的模擬、快速傅立業與反快速傅立業處理器的硬體共用、係數暫存器的縮小等等。

In order to design a general efficient FFT/IFFT core suitable for various OFDM communication systems, the thesis first investigates possible design solutions from algorithm level to architecture level. Following that, a variable-length memory-based FFT/IFFT architecture is proposed. The FFT/IFFT core can be applied to all the current OFDM-based FFT computation with sufficient throughput rate. Besides, the thesis also introduces some design methodologies for low hardware complexity realization that include word length simulation, complex multiplier design, ROM table size reduction and hardware sharing of FFT and IFFT, and etc.