低溫多晶矽薄膜電晶體之衰退機制分析以及新穎高性能元件結構之開發

Abstract

本論文主要分為二大部份： 一、 低溫多晶矽薄膜電晶體衰退機制之分析 二、 新穎高性能低溫多晶矽薄膜電晶體元件結構之開發 在第一部份，我們討論直流應力與交流應力對於低溫多晶矽薄膜電晶體造成衰退的機制。 在第二章，我們研究N型低溫多晶矽薄膜電晶體在直流應力之下，所發生的不規則關閉漏電流的變化。主要的機制可以歸因於：(1)由於通道熱電子在閘極氧化層/通道界面與矽晶粒邊界被捕捉，這些被捕捉的電子會增加電場因而導致漏電流的產生。(2)由於熱電洞在源極附近的通道/底層氧化層界面聚集/被捕捉，使得電場下降造成漏電流下降，在高汲極電壓的應力條件下，更多的電洞將因碰撞離子化效應而產生，同時，部份的電洞將會因汲極附近的高電場而被注入閘極氧化層，另外，部份的電洞將會因為受到橫向電場的影響由汲極向源極移動。 在第三章，我們討論低溫多晶矽薄膜電晶體在交流應力下衰退增加的機制，不同於在直流應力下所產生的最大電導單調下降趨勢，交流應力對於最大電導的影響起初是由於電洞注入汲極附近的閘極氧化層所造成通道縮減效應的影響，使得最大電導呈現上升的趨勢，之後，由於在閘極氧化層/通道界面與矽晶粒邊界上尾端缺陷的增加，使得最大電導呈現下降的趨勢。臨界電壓的變化，主要可由二個衰退機制來主導：(1)弱鍵結的斷裂，(2)具有與時間呈斜率0.4指數關係相依性的強鍵結斷裂。次臨界斜率的衰退機制，則可歸因於在矽晶粒內部所產生的缺陷。 在第四章，我們利用二種不同的交流應力條件來測試低溫多晶矽薄膜電晶體，相對於直流應力條件，我們可以發現交流應力對於低溫多晶矽薄膜電晶體會造成更大的衰退，在交流應力的條件下，所造成的衰退增加可歸因於：(1)在導通態下的碰撞游離化效應，(2)在關閉態下所產生的汲極雪崩熱載子效應，(3)暫態電流的應力效應。然而，在閘極電壓為-20V~20V、汲極電壓為0V的應力條件下，源極與汲極區都受到同樣的破壞，當下降時間縮短時，增加的暫態電流將造成在汲極附近更大的元件衰退，同時也發現短通道元件比長通道元件具有更大的衰退。當應力頻率增加時，衰退也隨之增加。在高溫應力的條件下，由於熱載子效應的降低，使得衰退也隨之減少。 在第二部份，我們提出三種新穎高性能的低溫多晶矽薄膜電晶體元件結構來有效地降低關閉漏電流，同時，相對於傳統低溫多晶矽薄膜電晶體具有100倍的改善。 在第五章，我們提出一種具有在汲極/源極附近擁有自我校準厚閘極氧化層的低溫多晶矽薄膜電晶體結構，此種新結構成功地被製造，同時，結果顯示此新結構具有約5.9X106的高導通/關閉電流比，也展現出在閘極電壓為-15V、汲極電壓為10V的條件下比傳統低溫多晶矽薄膜電晶體具有100倍以上的關閉漏電流改善。並且只需要4道光罩便可完成本結構，因此，本結構與傳統的低溫多晶矽薄膜電晶體製造流程完全相同，此新結構對於未來高性能大面積元件的應用，將是一個很好的選擇。 在第六章，我們提出二種具有副閘極耦合結構的新穎高性能低溫多晶矽薄膜電晶體，當在關閉態時，它的行為就如同位移閘極結構的低溫多晶矽薄膜電晶體，然而，當在導通態時，它的行為就如同傳統的無位移結構的低溫多晶矽薄膜電晶體。本新穎的低溫多晶矽薄膜電晶體具有比傳統低溫多晶矽薄膜電晶體具有100倍的關閉漏電流改善，同時本新穎的低溫多晶矽薄膜電晶體具有比位移低溫多晶矽薄膜電晶體還要高10倍的導通電流，而其導通電流也與傳統的低溫多晶矽薄膜電晶體導通電流相差不大，本新穎低溫多晶矽薄膜電晶體結構可以大幅地改善導通/關閉電流比約100倍。我們並不需要額外的光罩來產生此新結構的副閘極，同時，它的製程也與傳統無位移低溫多晶矽薄膜電晶體的製程完全相同。

This thesis can be divided into two major parts: (1) the analysis on the degradation mechanism of low temperature polycrystalline silicon thin film transistors (poly-Si TFTs), (2) the development of novel high performance structures for low temperature polycrystalline thin film transistors and In the first part, both static stress and dynamic stress on the degradation of low temperature poly-Si TFTs are studied. In chapter 2, we study the anomalous variations of OFF state leakage current (IOFF) in n-channel poly-Si TFT under static stress. The dominant mechanisms can be attributed to (1) IOFF increases due to channel hot electrons trapping at the gate oxide / channel interface and silicon grain boundaries. These trapped electrons increase the electric field that in turns, causes higher IOFF. (2) the decrease of IOFF can be attributed to hot holes accumulated / trapped near the channel / bottom oxide interface near source. At high drain bias, more holes will be generated by impact ionization and some of holes will be injecting into the gate oxide due to higher vertical field (~ (VGS-VDS) / TOX) near drain and some will be migrated from drain to source with higher speed due to larger lateral electric field (~ VDS / LCH). In chapter 3, we address the mechanisms responsible for the enhanced degradation in the polysilicon thin film transistors (poly-Si TFTs) under dynamic stress. Unlike the monotonic decrease of maximum transconductance (Gmmax) in static stress, Gmmax in dynamic stress is initially increased due to the channel shortening effect by holes injected into the gate oxide near the drain region, and then decreased due to tail states generation at the gate oxide / channel interface and grain boundaries. The threshold voltage variations are dominated by two degradation mechanisms: (1) breaking of weak bonds and (2) breaking of strong bonds to obey the power-time dependence law with a slope of 0.4. The degradation of the sub-threshold slope is attributed to intra-grain bulk states generation. In chapter 4, the dynamic stress on low-temperature processed polycrystalline silicon thin-film transistors (poly-Si TFTs) is studied under two different stress conditions. As compared to static stress, the enhanced degradation in poly-Si TFT can be observed in dynamic stress. The enhanced degradation in dynamic stress (Vgs = 0V~20V, Vds = 22V) is due to (1) the impact ionization effect in the ON state (Vgs = 20V, Vds = 22V), (2) the drain avalanche hot carrier effect in the OFF state (Vgs = 0V, Vds = 22V), and (3) the transient current stressing effect (at the switching period). However, in the stress condition of Vgs = -20 V ~ 20 V, Vds = 0 V, both the source and drain regions are equally damaged. As the falling time becomes shorter, the transient current will increase to cause more device degradation near drain. It is also found that the degradation is more serious in short channel device than that in long channel device. As the stress frequency increases, the degradation will be enhanced. Moreover, the reduced degradation under high stress temperature is due to reduced hot carrier effect under high temperature stressing. In the second part, three novel high performance device structures for low temperature poly-Si TFTs are proposed to effectively reduce the OFF state leakage currents by 2 orders of magnitude as comparing to the conventional poly-Si TFTs’. In chapter 5, a novel high-performance low temperature poly-Si TFT with a self-aligned thicker sub-gate oxide near the drain / source regions is proposed. Poly-Si TFTs with this new structure have been successfully fabricated and the results demonstrate a higher on / off current ratio of 5.9X106 and also shows the off-state leakage current 100 times lower than those of the conventional ones at VGS = -15 V and VDS = 10V. Only four photo-masking steps are required and fully compatible with the conventional TFT fabrication processes. This novel structure is a good candidate for the further high-performance large-area device applications. In chapter 6, we have proposed and fabricated two novel polysilicon thin film transistors (poly-Si TFTs) with a subgate coupling structure which behaves as an offset gated structure in the OFF state, while acting as a conventional non-offset structure in the ON state. The OFF state leakage current of these two new TFTs are two orders of magnitude lower than that of the conventional non-offset TFT, while the ON current of these two new TFTs are one order of magnitude higher than that of the offset TFT and is almost identical with that of the conventional non-offset TFT. The ON / OFF current ratio of the new TFT is greatly improved by two orders of magnitude. No additional photo-masking steps are required to fabricate the subgate of these two new TFTs and their fabrication processes are fully the same as the conventional non-offset TFTs’.