CMOS 125 MHz 雙絞線發射機

Abstract

本論文所設計之 CMOS 125 MHz 雙絞線發射機 (A CMOS 125 MHz Transmitter for UTP Cable) 主要是根據 十億位元乙太網路 (Gigabit Ethernet) 之系統規格而設計. 它主要包含兩個部份 : (1) 10 位元, 125 MHz 之數位類比轉換器 (Digital to Analog Converter, DAC) , (2) 1.8 V, 100 MHz , $-$42 dB THD 之傳輸線驅動器 (Line Driver) . 就數位類比轉換器而言, 為了能夠達到高速操作時脈的需求, 本論文採取電流切換式 (Current Steering) 數位類比轉換器之架構. 同時, 為了將佈局面積, 數位電路之速度與複雜度, 及差動非線性誤差 (Differential Nonlinearity Error) 做一最佳化之設計考量, 本論文採用一個等效於八位元之溫度計碼 (Thermometer Code) 解碼架構. 在降低整體非線性誤差 (Integral Nonlinearity Error) 的部份, 本論文根據製程漂移參數與所需良率等規格, 決定出最小所需的電流源佈局面積, 以期望能夠解決電流源隨機誤差 (Random Error) 的問題. 同時, 本論文採用二維距心式 (Two Dimensional Centroid) 之電流源開關切換順序, 適當的補償電流源的漂移, 以降低電流源因為線性誤差 (Linear Error) 與拋物線誤差 (Porabolic Error) 在開關切換的過程中所造成的誤差累積現象. 另外, 在電荷貫穿 (Charge Feedthrough) 及突波 (Glitch) 抑制的部份, 本論文利用緩衝器 (Buffer) 的概念, 分別在數位電路的輸出端與電流源的輸出端, 各加上一級的緩衝器, 利用緩衝器的阻絕, 降低電荷貫穿與突波的現象. 就傳輸線驅動器而言, 為了能夠得到較高的功率效益 (Power Efficiency) , 必須由輸出阻抗匹配電阻的去除與低電壓電路架構兩方面著手. 在輸出阻抗匹配電阻的部份, 為了解決輸出阻抗匹配電阻消耗一半輸出功率的問題, 因此, 採用合成 (Synthesis) 的方式, 產生輸出阻抗匹配電阻, 而且此合成電路並不會消耗任何的輸出功率. 在低電壓電路設計的部份, 本論文提出一種新式的 Class-AB 輸出級電路架構, 利用新的增益級負載, 解決輸出級電路電源電壓過高的問題, 而且此增益級負載在輸入訊號的振幅範圍內, 皆能夠維持高阻抗的狀態, 以避免因為輸入訊號的變動而影響低頻的諧波失真 (Harmonic Distortion) . 在高頻諧波失真抑制的部份, 本論文利用濾波電容及前饋路徑 (Feedforward Path) 的搭配運用, 對大寄生電容端點, 提供前饋的充放電路徑, 用以解決 Class-AB 的零交越失真 (Zero Crossover Distortion) 問題. 本傳輸線驅動器在 1.8 V 的電源電壓下, 能驅動 100 歐姆的輸出端負載, 產生 100 MHz , $-$42 dB THD , 2 $V_{pp}$ 的電壓訊號振幅, 而在此條件之下, 功率效益高達 37.3$\%$ , 且僅消耗 12 mW 的靜態功率.

This thesis describes a CMOS 125-MHz transmitter for UTP cable, which is based on Gigabit Ethernet system specification. The transmitter consists of, (1) a 10-bit, 125-MHz digital to analog converter (DAC), and (2) a 1.8-V 100-MHz $-$42-dB total harmonic distortion (THD) line driver. For high-speed application, the DAC adopts a current steering structure. With consideration for optimum layout area, complexity of digital circuit, and the differential nonlinearity error (DNL), the DAC consist of 8-bit thermometer-encoding and 2-bit binary-encoding. To reduce integral nonlinearity error (INL), the minimum area requirement for the current source is calculated based on process variation parameter to mitigate random error of current source. The 2-D centroid current source switching sequence is used to compensate the accumulation of current source variation which is caused by linear and porabolic process gradient. Buffers are used to isolate the output of digital circuit and current source to reduce the charge feedthrough and glitch. For the line driver design, this thesis focus on the impedance matching scheme and low voltage architecture to achieve high power efficiency. The utilization of impedance synthesis eliminates the impedance matching resistor which has extra power consumption. A novel low voltage Class-AB output structure is also demonstrated. A level-adaptive load is used to maintain large loop gain. A capacitive feedforward path is used to reduce crossover distortion. Operation under 1.8-V power supply, this line driver can deliver 100-MHz, 2-$V_{pp}$ voltage swing over a 100 $\upOmega$ differential load and achieve $-$42 dB THD. The power efficiency of the line driver is 37.3$\%$ , and consume 12mW quiescent power.