標題: 高效能管線化之直接數位頻率合成器設計
An Efficient Pipeline Direct Digital Frequency Synthesizer Based on a Novel Interpolation Algorithm
作者: 林孟學
Meng-Hsueh, Lin
陳紹基
Sau-Gee, Chen
電子研究所
關鍵字: 直接數位頻率合成器;DDFS;NCO
公開日期: 2001
摘要: 本篇論文提出一新式的直接數位頻率合成器,具有高速、低複雜度和高頻譜純度的特性。新式的直接數位頻率合成器是根據一新穎的內插演算法來達成正(餘)弦函數的計算,此新演算法精確地描述內插所造成的誤差。新式的直接數位頻率合成器藉著管線化的架構,不斷地執行內插以產生所要求得的數值,整個電路只需N個加法和一個大小為 字串的表即可,其中N為輸出值的位元長度。所需記憶體量與計算硬體面積比現有最佳同類型之數位頻率合成器少。模擬結果顯示當N=16時,SFDR可達到100dBc,而表的大小也只有304個位元。此外由於管線化架構的關係,新式的直接數位頻率合成器有很高的資料產生率和相當短、約一個加法延遲的時脈週期。
In this thesis, we propose a new direct digital frequency synthesizer (DDFS). It has the merits of high speed, low complexity and high spectrum purity. It is based on a novel interpolation algorithm for sinusoidal functions. The algorithm accurately characterizes the interpolation error. With a small lookup table of words, the DDFS successively interpolate the target value in a pipeline fashion using only N addition operations, where N is the output word length. Simulation shows that for N=16-bit example, 100dBc of SFDR (spurious free dynamic range) is achieved, with a lookup table of only 304 bits. In addition, due to its pipeline structure, the new DDFS have a very high throughput rate and a very short cycle time of about an adder delay. The new design has a smaller table size and less datapath requirement than the best known DDFS by Madisetti et al, at the same speed performance.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT900428142
http://hdl.handle.net/11536/68830
顯示於類別:畢業論文