以改良式冗餘算術座標旋轉演算法所設計之直接數位頻率合成器

Abstract

在本篇論文中，我們將探討將座標旋轉(CORDIC)演算法與其在直接數位頻率合成器(DDFS)上的應用。CORDIC是一種可以利用移位器與加法器來處理旋轉運算的演算法，然而二進位的CORDIC處理器的速度瓶頸受限於加法器的進位傳遞，利用冗餘二進位(redundant binary)算術法即可改善此問題。在本論文中我們提出二個較有效率之改善架構，基本的構想是要減少角度旋轉運算的範圍以使旋轉運算級減少，然而因為旋轉範圍減小，所以還需要額外的查表器來儲存旋轉的起始點，這個構想我們以雙旋轉法與重新編碼法來實現。最後這二種改良的架構皆由Verilog硬體描述語言設計，並藉由Avant! 0.35μ標準電路單元以Synopsys合成工具合成。在原有八級的設計下移除前二級的旋轉級，分別可以節省硬體面積達30%與50%以上。在適當的路徑下使用管線式架構，使得此二種改良架構皆可在350MHz的時脈頻率下正常運作。

In this thesis, we discuss the CORDIC algorithm and its applications on the direct digital frequency synthesizer (DDFS). The CORDIC algorithm is a well-known iterative method for the vector rotation computations, which can be implemented by regular shifters and adders. However, the throughput of conventional binary arithmetic CORDIC processor is limited by the carry-propagation of the adders. Recent researches have taken advantage of the carry-free characteristic of redundant number arithmetic to speed up CORDIC operations. In this thesis, we propose two efficient redundant CORDIC algorithms. Our idea is to reduce the angle rotation range such that the number of processing stage can be reduced. Since the rotation range is reduced, multiple initial vectors are required, which are stored in a lookup table. This idea is then realized using the double rotation and recoding CORDIC algorithms. Finally, the two proposed architectures are designed by Verilog hardware description language, and then synthesized by Synopsys Design Complier using Avant! 0.35μm standard cell library. Removing two stages from original designed eight-stage-CORDIC, we can reduce the hardware area more than 30% and 50%, respectively. Both architectures can be operated in 350MHz clock frequency using appropriate data-path pipelining.