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dc.contributor.authorLin, Po-Chingen_US
dc.contributor.authorLin, Yin-Daren_US
dc.contributor.authorLai, Yuan-Chengen_US
dc.contributor.authorZheng, Yi-Junen_US
dc.contributor.authorLee, Tsern-Hueien_US
dc.date.accessioned2014-12-08T15:09:03Z-
dc.date.available2014-12-08T15:09:03Z-
dc.date.issued2009-08-01en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TVLSI.2008.2012011en_US
dc.identifier.urihttp://hdl.handle.net/11536/6887-
dc.description.abstractMany network security applications rely on string matching to detect intrusions, viruses, spam, and so on. Since software implementation may not keep pace with the high-speed demand, turning to hardware-based solutions becomes promising. This work presents an innovative architecture to realize string matching in sub-linear time based on algorithmic heuristics, which come from parallel queries to a set of space-efficient Bloom filters. The algorithm allows skipping characters not in a match in the text, and in turn simultaneously inspect multiple characters in effect. The techniques to reduce the impact of certain bad situations on performance are also proposed: the bad-block heuristic, a linear worst-case time method and a non-blocking interface to hand over the verification job to a verification module. This architecture is simulated with both behavior simulation in C and timing simulation in HDL for antivirus applications. The simulation shows that the throughput of scanning Windows executable files for more than 10 000 virus signatures can achieve 5.64 Gb/s, while the worst-case performance is 1.2 Gb/s if the signatures are properly specified.en_US
dc.language.isoen_USen_US
dc.subjectAlgorithmsen_US
dc.subjectfield-programmable gate arrays (FPGAs)en_US
dc.subjectstring matchingen_US
dc.titleRealizing a Sub-Linear Time String-Matching Algorithm With a Hardware Accelerator Using Bloom Filtersen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TVLSI.2008.2012011en_US
dc.identifier.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSen_US
dc.citation.volume17en_US
dc.citation.issue8en_US
dc.citation.spage1008en_US
dc.citation.epage1020en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000268282700004-
dc.citation.woscount8-
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