W-CDMA空-時接收機時序與頻率同步器之DSP與FPGA實現

Abstract

在第三代行動通訊技術中，W-CDMA (Wideband Code Division Multiple Access)佔有關鍵性的地位，它採用分碼多重進接技術技術，並利用頻率重複使用之優點，能有效增加系統容量。在本論文中，吾人利用Aptix® MP3C硬體平台整合DSP (Digital Signal Processor)、FPGA (Field Programmable Gate Array)與部分類比元件，完成W-CDMA接收機軟硬體架構實現。近年來，DSP與FPGA在數位資料處理上，各扮演重要的角色，DSP擁有強大的運算能力，提供高速之浮點及定點運算，足以應付即時的訊號處理；另一方面，FPGA為一可程式化邏輯元件，利用硬體描述語言合成數位邏輯電路，提供快速之硬體驗證。吾人之接收機架構中包含碼擷取電路、碼追蹤迴路電路、延遲路徑搜尋器、解展頻器、自動頻率控制器與犁耙接收器等功能，最多可以搜尋三個不同延遲路徑並同時解展頻，且可以估計並補償傳送端與接收端之頻率偏移。本論文結合了DSP與FPGA實現接收機之軟硬體架構，在硬體電路面積與軟體運算時間取得最佳化分配，並導入軟體無線電概念，藉由改變DSP程式，可輕易置換系統之核心演算法，藉以降低電路設計之複雜度並提昇系統之可適性。

W-CDMA has become a key technology in the third-generation mobile communication systems. Based on the CDMA scheme, W-CDMA can effectively increase the system capacity by a tight frequency reuse. In this thesis, we will realize the W-CDMA baseband receiver by integrating DSP, FPGA and some analog devices on the Aptix® MP3C hardware platform. In recent years, DSP and FPGA have played important roles in digital signal processing. DSP is a powerful processor with high speed floating-point or fixed-point operation, which is suitable for real-time signal processing. FPGA is a programmable logic device, which can be used to design digital logic circuits by hardware description language and provide quick hardware verification. Our baseband receiver includes a code acquisition circuit, a code tracking loop circuit, a finger searcher, a despreader and an auto frequency controller. It can search for three delayed paths and despread them in parallel, and can also estimate the frequency offset and compensate for it. The thesis takes aim at integrating DSP and FPGA to realize the software/hardware architecture of the receiver, and achieving a best trade-off between the hardware circuit area and software run time. With the concept of soft-defined radio incorporated, we can easily replace the system core algorithms by rewriting DSP programs. This can help to reduce the circuit design complexity and increase the flexibility of the system.