利用去耦合電容與RC終端改善印刷電路板電源切換雜訊

Abstract

隨著電子技術不斷進步，時序脈波信號愈來愈快，電磁干擾問題也日益嚴重。電源系統是產生電磁干擾與傳播電磁干擾的一個重要機制。在多層電路板中，通常具有專屬的電源層與接地層作為系統電源與信號回流路徑之用。 本文將以二維傳輸線模型來建立電源層/接地層的Spice模型，並且利用該模型探討數位電路邏輯準位切換電流在電源層上產生的電源雜訊、以及使用去耦合電容、RC 終端、改變電源層/接地層高度等方法，抑制電源上的雜訊。

With the fast increase of chip clock frequency, the high frequency noise on power distribution network caused by simultaneous switching is a primary source of electromagnetic interference and signal integrity problems in high-speed digital circuit design. In multilayer printed circuit board, it is a common practice to use dedicated power and ground planes for power distribution network. In this thesis, we first use two dimensional transmission lines for the simulation and modeling of power and ground planes. With this model, the noise on the power distribution network caused by simultaneous switching can be easily evaluated. We then investigate the effectiveness of using decoupling capacitors , RC termination and changing the spacing between power and ground planes for the suppression of the noise on the power distribution network.