Triple-DES及AES加密演算法的硬體設計與實現

Abstract

隨著網際網路的快速發展，網路安全的課題也日益受到重視。資料加密是提供網路安全的一項重要技術，而Triple-DES是目前最廣泛使用的加密演算法，AES則是用來取代DES的下一代加密演算法。隨著網路傳輸技術的進步，不論何種加密演算法，過去利用軟體提供加密功能的技術，已經無法滿足目前網路的傳輸速度。 在這篇論文中，利用Altera公司的FPGA平台實現Triple-DES及AES加密演算法，並提出一種新的Triple-DES硬體架構，此架構能有效增進目前Triple-DES的處理速度。我們選擇利用FPGA實現的原因在於它較有彈性，可針對不同環境調整不同的架構，並可有效加快加密演算法的處理速度。FPGA結合了硬體處理速度的優點及軟體的彈性，配合不同環境所需的架構作適當調整，可使加密處理滿足寬頻時代的速度要求，同時也能配合不同演算法的產生做適當的調整，有效的滿足實際的需求。

With the rapid growth of the Internet applications, network security becomes as an important issue. Data encryption is one of the essential technologies when implementing the network security. Triple DES is amongst the most widely known, trusted and used nowadays; as to AES, it’s the one that will replace the DES and become as the next generation encryption algorithm. Due to the great progress made by the network transmission technology, software implementation of encryption algorithms in that past decade couldn’t satisfy the high-speed network transmission. Hence, no matter what kind of encryption technologies are adapted, construct cryptographic accelerators using hardware implementation is necessary in the future. In this thesis, we implement the Triple-DES and AES encryption algorithms via the Altera FPGA board. Besides, we propose a novel hardware architecture implementation of the Triple DES encryption algorithm. This new architecture can increase the processing speed much more than the other commercial ones. The reason why we implement our Triple DES and AES on the FPGA board is its two characteristics: high-processing speed and flexible programming environment. As a result, we could optimize our architectures according to either the algorithm itself or different environment variables and satisfy the demand in reality.