針對安全性嵌入式系統之彈性管線化設計與實做

Abstract

在現今的環境中，提供加密的需求已是刻不容緩，如果在嵌入式系統中加入加密的運算，就會遇到幾項議題，其中我們針對處理速度以及硬體彈性這兩項議題進行討論，我們針對目前較常見的加密演算法，分別為AES DES 和RSA。提供一個可在AES，DES和RSA之間彈性轉換，並且可以彌補速度上不足之硬體。在考量處理速度不足這項議題之下，我們採用速度與面積乘積為評比標準。

在本論文中，我們首先分析此三演算法之運算需求，然後針對不同類型之運算分別設計出排列組合單元，運算單元以及記憶單元，其中排列組合單元採客制化設計，運算單元由處理單元所組成，記憶單元則由單位緩衝區所組成，我們討論處理單元以及單位緩衝區的設計以及考量在不同比例之運算單元以及單位緩衝區之下，造成面積速度乘積的影響，最後所提出的設計和針對個別演算法之客制化設計做比較，比較結果顯示我們的方法確實在面積速度乘積有較好的效果。

Providing security has become more and more urgent and necessary in embedded systems. If we want to support security in our embedded systems, some issues must be solved. We focus on processing gap and flexibility concerns. We target on the three commonly used cryptographic algorithms, AES, DES and RSA. In our thesis, we want to propose a hardware which solves the processing gap and switches flexibly between AES, DES, and RSA. Under the consideration of processing gap, we use space-time product as our performance metrics.

We first classify the operation of the three cryptographic algorithms into three classes. Then, we design modules for different operation classes respectively. The three modules are permutation-combination unit, computation unit and memory unit. The permutation- combination unit is a custom design. The computation unit is consisted of processing elements and the memory unit is consisted of tile buffers. The different ratio of processing elements and tile buffers will lead to different results. We choose the most appropriate ratio. Finally, our proposed method will get better result than ASIC design.