應用於無線感測網路之超低耗能連續近似式類比數位轉換器之設計

Abstract

隨著製程及設計技術的進步，在電路速度方面已有顯著的提升，例如電腦中央處理器(CPU)之操作已達到3GHz以上。然而，對於可攜式裝置、感測器及生物應用來說，操作時間的長短卻遠比速度的快慢來得重要，例如以野生動物偵搜應用，由於其更換電池不易，故需以低耗能之設計來加長操作時間。

本論文提出利用0.18微米互補式金氧半製程實現一應用於無線感測網路之0.9伏特及8位元超低耗能連續近似式類比數位轉換器，此類比數位轉換器結合了靴帶式(Bootstrapping)及接地式開關(Grounded-switches)的技巧來減少功率消耗。在低供應電壓下，為了改善訊號雜訊比值，故提出一個有軌對軌輸入的比較器來使類比數位轉換器有軌對軌的輸入。量測結果呈現在輸出頻率為144KS/s時，此連續近似式類比數位轉換器有著軌對軌(Rail-to-rail)的輸入及其訊號對雜訊諧波比為46.67dB，且有效解析度頻寬可以到達奈奎斯頻率(72KHz)，而此類比數位轉換器之功率消耗只有2.16μW，此時之FOM (Figure of merit)可達0.08pJ/conversion-step，此數值比我們所知文獻之FOM好上22倍之多，為目前最低之FOM。

Following the progress of fabrication process and design skills, the circuit speed has been remarkably promoted. For instance, the center processor unit (CPU) can be operated above 3GHz. For energy-limited applications such as the portable amusement, sensors, and biometrics, a longer operation time is the major concern rather than the speed. For instance, an animal tracking system is expected to sustain for several years as a result of being hard to replace the battery.

This paper presents a 0.9V, 8-bit ultra low power successive approximation analog-to-digital converter for wireless sensor networks in 0.18μm 1P6M CMOS process. The analog-to-digital converter utilizes both bootstrapping and grounded-switches techniques to save the power consumption. A comparator with a rail-to-rail input range is proposed to make the input range of the ADC also rail-to-rail. Measurement results show that under an output rate of 144KS/s, the SA ADC has a rail-to-rail input range and a peak signal-to-noise-distortion ratio (SNDR) of 46.67dB with an effective resolution bandwidth (ERBW) up to the Nyquist frequency (72KHz). Its power consumption is as low as 2.16μW corresponding to a figure of merit (FOM) of as low as 0.08pJ/conversion-step. The FOM is 22 times better than the best one of the state-of-the-art works as far as we know.