低位元率語音編碼專用處理器

Abstract

語音傳輸是目前最主要也最普遍的通訊傳輸服務。在數位語音下的傳輸更有彈性，能夠降低價格、維持品質並提供保密的功能。由於使用者的增加與有限的頻寬，新的語音編碼傳輸位元率已由8Kbps（CELP）與4.8Kbps（CS-ACELP）發展至2.4Kbps（MELP）。也因為傳輸位元率的降低，語音品質就只能由更複雜的演算法來提昇，這使得實現快速語音編解碼相當困難。 本論文針對壓縮率相當高的MELP，提出一個新的語音編碼技術處理器，使用軟體—硬體雙重設計的方式使處理器的架構與指令集最佳化。處理器中使用五級的管線式架構來平衡處理速度與晶片面積，同時擁有兩個向量處理用的記憶體、四層迴圈、大範圍的記憶體資料暫存區、24 bits精確的浮點運算單元、整數運算單元、提供很大動態運算範圍8 bits的指數處理單元以及具有平行處理能力的指令。在指令長度固定為24 bits下，此處理器提供6種定址模式與三元運算。 此晶片以Cell-Based方式設計完成，使用TSMC 0.35μm製程之標準元件庫，預估能工作於60 MHz。晶片面積約為10.22㎜2。

Speech communication is the most dominant and common service in telecommunication at present. Digital transmission of speech is more elasticity, providing the opportunity of achieving cost, consistent quality, security and spectral efficiency in the systems that exploit it. Due to the increase in number of users and limited bandwidth available, the transmission rate of new digital speech coding techniques has dropped from 8Kbps（CELP）, 4.8 Kbps（CS-ACELP）to 2.4Kbps（MELP）. As the bit rate falling, the speech quality can only be maintained by employing very complex algorithms which are difficult to implement in fast speech coding. This thesis investigates a new application specific processor for speech coding processing. The processor is designed to process Mixed Excitation Linear Prediction（MELP） coding which is the best and common speech compression. We use hardware-software codesign methodology to optimize the processor architecture and instruction set. The processor uses a five-stage pipeline to balance performance and core area. It has two memory banks for vector operation, four-level recurrent loops, multi-layer stacks, 24-bit floating-point unit for precision, integer unit, 8-bit exponent unit for large dynamic range operation and special instructions for parallel operation. Each instruction length is fixed as 24 bits. The processor provides six special addressing modes and 3-operand operations. The chip is realized by using a TSMC 0.35μm 1P4M CMOS fabrication and synthesis by COMPASS cell library. The clock rate of the chip is expected to be 60 MHz and the silicon area required for the core is approximately 10.22㎜2.