一數值赫夫曼解碼器之實現

Abstract

目前應用在影音訊號之壓縮標準，如JPEG、MPEG都會使用到赫夫曼解碼器。由於赫夫曼碼碼長不一的特性，赫夫曼碼解碼器設計不易。現今存在的赫夫曼解碼器，大部分皆以資料結構觀點進行赫夫曼解碼。本實驗室於去年針對赫夫曼解碼法提出另一看法，將赫夫曼碼看成一數值序列，然後以數值分析的方法來解碼，我們稱之為「數值赫夫曼解碼器」，此方法既可快速解碼而且記憶體需求小。本篇論文承襲上述的數值赫夫曼解碼理論，提出一硬體架構來實現此數值赫夫曼解碼器。本次實現的解碼器，可處理赫夫曼碼的長度最長為16位元，主要的運算單元為一個「加法器」和一個「位移暫存器」，再配合五個「多工器」與十二個「暫存器」即可實現。另外，我們依照「特殊應用積體電路的設計流程（ASIC Design Flow）」，對我們所設計的硬體架構進行模擬驗證。最後，我們並結合FPGA實驗板與電腦印表機傳輸埠來進行此解碼器的實體驗證。以證明我們所提出的數值赫夫曼解碼理論，其解碼功能正確且實現低複雜度的優點。

The compressing standard on audio and video signals, such as JPEG or MPEG, includes the function of Huffman decoder. Decoding Huffman code is difficult because of the inherent property of varying code length. Existing algorithms for Huffman decoder are developed based on the data structure of Huffman codes. Using a new perspective to treat the Huffman code as a numerical sequence, we have designed a new Huffman decoder, referred to as the numerical Huffman decoder, which, compared with existing algorithms, has a better performance on decoding speed and realization complexity. This thesis proposes a hardware architecture to realize the numerical Huffman decoder. We aims to develop a hardware Huffman decoder for Huffman codes of 16-bits maximum length. The major hardware includes an adder and a shift-register, along with five multiplexers and twelve registers. Besides, we have followed the ASIC design flow to present an IC for the Huffman decoder. Finally, the decoding function is verified by combining the hardware decoder with printer-port transmission in an FPGA board.