以掃描探針微影術及非等向性濕式蝕刻製作矽奈米結構

Abstract

矽奈米結構具有特殊的光子性質元件，在光積體系統(photonic integrated circuits)扮演重要的角色。然而提供奈米等級的設備與裝置都極為昂貴，以致阻礙奈米光子元件在研究室中的開發。掃描探針微影術(scanning probe lithography)是一新興之技術，以臨近樣品表面的探針引致局部陽極氧化反應(掃描探針氧化反應，scanning probe oxidation)，提供與先進微影技術可相媲美的解析度，且具備簡單性、普遍性與低成本等優點，被視為發展奈米元件的關鍵技術。此一研究的目的在開發一植基於掃描探針微影術的製作技術，可靠又能被研究單位負擔的，以從事原型奈米光子元件之研發。 我們成功地以掃描探針微影術在奈米尺度將氮化矽轉變氧化矽。掃描探針氧化反應之成長運動學(growth kinetics)遵守對數關係，而且成長速率對應於氧化矽高度呈指數衰減。我們發現氮化矽的掃描探針氧化反應只需很短的起始時間(onset time)，造成它有極高的初始氧化速率。靜電力檢測(electrostatic force characterization)結果顯示有正電荷局限在探針引置之氧化矽之中，而且電荷的數量與氧化矽的高度呈線性關係。因此推論局限電荷造成氧化反應的活化能增加，亦即導致成長速率呈指數降低之原因。 藉由矽在氫氧化鉀(KOH)及四甲基銨氫氧化物(tetra-methyl ammonium hydroxide，TMAH)中的非等向性蝕刻，我們製作多種矽結構在不同之晶片(矽晶片、氮化矽成長之矽晶片(Si3N4-coated Si wafer)及SOI (silicon on insulator))，如100 nm線距之結構、正對比與負對比之結構、400 nm縱深結構。利用方格型的遮罩，被六個矽晶面包圍自我終止(self-limited)的六角形凹槽被製作在(110)矽晶片上。由六角形凹槽的形成，得知凹槽的形狀與方格之大小及方向有密切關係。我們認為以掃描探針微影術配合非等向性濕式蝕刻(anisotropic wet etching)是一種可在不同的矽晶片上製作平滑且均勻之矽奈米結構的方法，又具備低成本及可靠的特性。 我們成功地將掃描探針微影術與傳統光學微影術結合成一複合式多層微影技術，以實現光子元件所需求的微米與奈米結構。此一複合式微影技術配合非等向性濕式蝕刻可望成為迅速開發奈米光子元件原型的可行方法。基於此一研究所建立之技術，我們提出一在SOI上製作一維光子晶體(photonic crystal)的製程。

Si nanostructures offering unique photonic properties are significant to the applications of photonic integrated circuits. However, the extremely high expenses of the facilities and utilities to provide nanometer scale features have blocked the development of nano photonic devices in research laboratories. Scanning probe lithography (SPL), employing a proximal probe to induce local anodic oxidation (so-called scanning probe oxidation), can provide nanometer lateral resolutions comparable to most advanced lithography and exhibit the distinction of simplicity, generality and low cost. The aim of this study is to develop a reliable, yet affordable technique for rapid prototyping of nano photonic devices in laboratories based on SPL. We demonstrated the conversion of Si3N4 to SiOx at the nanometer scale can be performed by SPL. The growth kinetics of scanning probe oxidation on Si3N4 obeys the logarithmic relationship and growth rate exponentially decays with respect to oxide height. We found scanning probe oxidation of Si3N4 has a short onset time, which accounts for its extremely high initial oxidation rate. Electrostatic force characterization indicates that charges, trapped in probe-induced oxide, are positive and linearly increase with the oxide height. We suggest that effective activation energy of oxidation increases with the amount of trapped charges, and therefore the exponential decay of growth rate can be derived. By means of Si anisotropic etching in KOH and tetra-methyl ammonium hydroxide (TMAH) etchants, we produced a variety of Si structures with the oxide patterns on either Si or Si3N4 as masks. They include structures with a pitch of 100 nm, structures of positive and negative contrast, and features height greater than 400 nm, produced on bare silicon, Si3N4-coated silicon and silicon-on-insulator (SOI) wafers. Evolution of hexagonal pits on two-dimensional grid structures is shown to depend on the pattern spacing and orientation with respect to silicon crystal directions. We conclude the process of SPL in combination with anisotropic wet etching (KOH or TMAH) is a low-cost and reliable method to produce smooth and uniform silicon nanostructures on different Si substrates. We have succeeded in the combination of SPL with traditional optical lithography as a mixed, multilevel patterning method for realizing micrometer- and nanometer-scale feature sizes, as required for photonic device designs. We believe the cooperating method of the combined lithography and anisotropic wet etching is a promising approach for rapid prototyping of functional nano photonic devices. Based on the techniques developed in this study, a process to fabricate 1-D photonic band gap on SOI is proposed.