VDL Mode 2接收機架構之研究及DSP實現

Abstract

軟體無線電架構的發展，近幾年來已成為一個極受矚目的研究領域。本論文首先將介紹軟體無線電(software-defined radio)平台之概念，進而將此概念，實際應用在特高頻數位鏈結模式2 (VHF Digital Link Mode 2, VDL Mode 2) 的數位多模式無線電 (Digital Multi-Modes Radio, DMMR) 上。在VDL Mode 2的實體層 (physical layer)中，未編碼位元錯誤率 (uncoded BER) 是評估VDL Mode 2接收機性能的一個重要指標，而這個指標又與載波頻率能否有效回復 (recovery) 有密切關係。因此吾人必須找出一種簡單、快速且有效的頻率估計方法，並經由模擬來驗證此方法能否符合VDL Mode 2的規範。根據模擬結果顯示，吾人所使用之演算法可完全符合VDL Mode 2的規範，且只要再經少許修改，即可向後繼續延伸至VDL Mode 3與VDL Mode 4。此外，論文中亦將介紹TMS320C5410 DSP數位信號處理器之硬體架構，與其軟硬體設計，並將已發展完成之里德–所羅門碼(Reed–Solomon code)載入其中，評估數位信號處理器 (DSP processor) 的處理能力。此外吾人亦將說明如何運用可程式場閘陣列 (field programmable gate array, FPGA)、ARM微處理器與DSP處理器 三者所結合的平台，來實現VDL Mode 2接收機。

Recently, the development of software-defined radio has been a fascinating research area in wireless communication signal processing. In this report, we will first introduce the concept of software-defined radio, and then apply the concept in the DMMR (Digital Multi-Modes Radio) of VDL (VHF Digital Link) Mode 2. In a practicing view of VDL Mode 2, the uncoded BER is an important index to evaluate the performance of VDL Mode 2 receiver, and it also has close relationship with the recovery rate of carrier frequency. Therefore, we have to find a simple, rapid and efficient method of frequency estimate to prove whether the method can meet the requirement of the specification of VDL Mode2 through simulation. According to the result of simulation, our algorithm can perfectly match the specification of VDL Mode 2. With a little more modification, it can further apply to the VDL Mode 3 and VDL Mode 4. In addition, we will introduce the architecture of TMS320C5410 DSP, and show how to design the hardware and software, and then load the developed Reed–Solomon code into our design to evaluate the performance of DSP. Furthermore we will integrate the FPGA (Field Programmable Gate Array)、ARM microprocessor and DSP processor to implement the receiver of VDL Mode 2.