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dc.contributor.authorLee, CYen_US
dc.contributor.authorLu, MCen_US
dc.date.accessioned2014-12-08T15:01:58Z-
dc.date.available2014-12-08T15:01:58Z-
dc.date.issued1997-03-01en_US
dc.identifier.issn0922-5773en_US
dc.identifier.urihttp://hdl.handle.net/11536/696-
dc.description.abstractThis paper presents a novel memory-based VLSI architecture for full search block matching algorithms. We propose a semi-systolic array to meet the requirements of high computational complexity, where data communications are handled in two styles: (I) global connections for search data and (2) local connections for partial sum. Data flow is handled by a multiple-port memory bank so that all processor elements function on target data items. Thus hardware efficiency achieved can be up to 100%. Both semi-systolic array structure and related memory management strategies for full-search block matching algorithms are highlighted and discussed in detail in the paper.en_US
dc.language.isoen_USen_US
dc.titleAn efficient VLSI architecture for full-search block matching algorithmsen_US
dc.typeArticleen_US
dc.identifier.journalJOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGYen_US
dc.citation.volume15en_US
dc.citation.issue3en_US
dc.citation.spage275en_US
dc.citation.epage282en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1997XE96800006-
dc.citation.woscount6-
Appears in Collections:Articles


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