積體電路製程中考慮多種變異來源之缺陷點數管制流程

Abstract

在晶圓製造過程中，缺陷點（defect）的發生是不可避免的，由於缺陷點對晶片的品質有很大的影響，因此在晶圓製造過程中缺陷點的數量必須加以管制才能達到預期的晶圓品質。此外隨著晶圓製造技術的精進，晶圓的面積越作越大，晶圓表面的缺陷點開始出現羣聚（clustering）現象，由於此羣聚現象會讓管制結果出現缺陷點數多寡和晶片良率高低不符合的狀況，因此在管制晶圓缺陷點時羣聚現象也必須加以考慮。目前積體電路製造廠是採用每一批量抽取一片晶圓量測其缺陷點數再使用缺陷點數管制圖（c-chart）來管制晶圓缺陷數，由於此種方法無法偵測出製造過程中的晶圓間變異（wafer-to-wafer variation）及批量間變異（lot-to-lot variation）而且也沒有考慮缺陷點的羣聚現象，以致管制效果不佳。目前雖然已有文獻提出管制量測性質的品質特性的三種變異來源，但是是針對量測性質的品質特性，所以並不適用於管制缺陷點數。本研究之主要目的即是針對晶圓製造過程中所產生的缺陷點之數量，建構出一個能考慮多種變異來源的管制圖，並利用多變量分析中的階層式羣集法（Hierarchical Clustering Method）修正晶圓上缺陷點的羣聚現象，構建出一套完整有效的管制流程。本研究最後以模擬之案例說明管制流程，並驗證所建構之管制流程確實能有效管制缺陷點數並追溯其變異是來自晶圓與晶圓間或是批量與批量間，提供發生缺陷點的不同變異來源及消除羣聚現象對於晶片良率的影響，讓線上人員能針對問題原因提出修正改善的方案而獲得較佳的管制結果。

In integrated circuit (IC) fabrication, the appearance of wafer defects is unavoidable. Because defects influence the yield of a wafer, it is necessary to control defects to enhance the wafer quality. A Poisson distribution based c-chart is generally utilized to monitoring the wafer defects. However, the wafer size increases as IC fabrication techniques improve in the recently years, defects on wafer surface appear cluster phenomenon. The defect clustering will cause too many false alarms in the c-chart. In addition, the IC manufacturers usually obtain the defect counts from just one wafer sampled from a lot of twenty-five wafers to construct the c-chart. In such case, the wafer-to-wafer variation cannot be detected. The purpose of this study is to develop a procedure in which three control charts are included. An individual control chart and a moving range control chart are constructed to detect the wafer-to-wafer variation based on the modified defect counts using hierarchical clustering method to reduce the clustering impacts on the total number of defects. A c-chart is then employed to monitor the lot-to-lot variation if the wafer-to-wafer variation is stable. Cases to with simulated data are illustrated to verify the effectiveness of the proposed procedure.