完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 黃信榮 | en_US |
dc.contributor.author | Hsin-Jung Huang | en_US |
dc.contributor.author | 鍾淑馨 | en_US |
dc.contributor.author | 彭文理 | en_US |
dc.contributor.author | Shu-Hsing Chung | en_US |
dc.contributor.author | Wen-Lea Pearn | en_US |
dc.date.accessioned | 2014-12-12T02:29:53Z | - |
dc.date.available | 2014-12-12T02:29:53Z | - |
dc.date.issued | 2002 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT910031067 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/69827 | - |
dc.description.abstract | 本文以半導體末段製程之記憶體IC最終測試廠為研究對象,考量其主要生產特性,包含:訂單式代工服務、多產品等級、測試製程迴流、序列相關設置時間以及批次作業等特性。半導體最終測試廠最重視之營運目標為顧客滿意度,主要取決於訂單是否準時達交。因此,本文以最小化延遲工單數為衡量指標,構建一主生產排程規劃系統。 本文發展之模式分為三部份,首先針對規劃週期內之需求,以產能負荷平準化為原則,構建線性規劃模式,並將規劃週期內預定完成之產品數量指派予各機群。接著,以等候理論為基礎,根據前一階段規劃之各機群分配情況,預估各產品各等級之生產週期時間,並藉此估算值設定各工單之內部交期。最後以固定在製品投料法,考量各工單交期緊迫度及機群當時負荷狀況,設定現場投料及派工之準則。 透過粗略產能規劃階段均勻分配各機群之產能負荷,配合主生產排程階段之生產週期時間估算以及現場投料規劃,可迅速產生一生產排程。模擬結果顯示,經由以上三階段之生產規劃與控制流程,各工單之達交比率可以達到相當良好之成果。 | zh_TW |
dc.description.abstract | This research consider the construction of master production planning system for the memory IC final testing process in wafer fabrication, which includes such properties as make-to-order OEM services, multiple-priority orders, reentrant flow in final testing process, sequence dependent setup time, and batch operation. The most important performance criteria for IC final testing factories relates to customer satisfaction, which is measured by the on- time delivery of orders. Consequently, this research aims to construct a master production planning system with the minimization of the number of delay orders. The construction of master production planning system consists of three phases. First, according to the order demands in the planning horizon and the rule of balanced capacity loading, a linear programming model, developed in this research, is used to allocate the capacity of workstations to products. Second, based on the queuing theory and the allocation results in the first phase, estimates the production cycle time for all product type in all priorities. Furthermore, the estimated production cycle time will be regarded as the internal delivery due-date of lots. Finally, considering the priority of each lot and the capacity loading status of workstations, and according to constant WIP releasing, selects suitable releasing rules or dispatching rules in the shop floor. The rough-cut capacity planning (RCCP) developed in the first phase balances the capacity loading of workstations. The master production planning (MPS) developed in the second phase determines the estimation of product cycle time. The three phases master production planning system generates a production schedule. The simulation results show that the three phases master production planning system performs well in the criteria of on- time delivery ratio. | en_US |
dc.language.iso | zh_TW | en_US |
dc.subject | 最終測試 | zh_TW |
dc.subject | 製程規格能力 | zh_TW |
dc.subject | 生產排程 | zh_TW |
dc.subject | final testing | en_US |
dc.subject | process capability | en_US |
dc.subject | production scheduling | en_US |
dc.title | 記憶體IC最終測試廠主生產規劃系統之構建 | zh_TW |
dc.title | The Construction of Master Production Planning System for Memory IC Final Testing Factories | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 工業工程與管理學系 | zh_TW |
顯示於類別: | 畢業論文 |