具重新配置效益且節省記憶體的802.11n低密度奇偶校驗碼解碼器

Abstract

本論文主要是針對M. M. Mansour.與N. R. Shanbhag所提出的 TDMP LDPC解碼演算法及其硬體架構加以改良，以期用些許的編碼增益來換取更高的可重新配置性並節省更多的記憶體。一般而言，由於M. M. Mansour與N. R. Shanbhag所提出的演算法是採取類似渦輪碼的解碼方式，其利用BCJR演算法來取代傳統的兩段式位元節點與校驗節點之訊息傳遞，因此其所提出來的TDMP LDPC解碼演算法可以比傳統的和積演算法減少75%以上的記憶體需求。再者，其演算法的收斂速度較快，也因此可以提供更高的解碼速率。而其在硬體上所提出的架構，不論在功率上或者是內部連結上，也都比傳統的和積演算法所對應的架構來的有效率。而本論文就是基於此種解碼演算法與硬體架構，在不損失上述優點的前提之下，利用遺忘因子(forgetting factor)的方式，將其演算法與硬體架構加以改良，使其記憶體可再節省50%以上，並大大地增加硬體架構上的可重新配置效益。

This thesis presents a modified version of the TDMP (Turbo Decoding Message Passing) LDPC (Low Density Parity Check) decoding algorithm which was proposed by Mansour and Shanbhag [18] in 2002. The goals of this research are to reduce the memory requirement of the TDMP LDPC decoder with a minor loss of coding performance. In the TDMP LDPC decoder, the turbo decoding message passing algorithm, which utilizes the BCJR algorithm, is used to remove the multiple "check-to-bit" message update bottleneck of the traditional Sum-Product LDPC decoding algorithm. The TDMP algorithm can reduce at least 75% memory requirement compared with the Sum-Product algorithm. In addition, the TDMP algorithm exhibits a faster convergence behavior than the Sum-Product algorithm. Thus, high decoding throughput and low power consumption can be expected for the TDMP LDPC decoder. In this thesis, a modified TDMP LDPC decoding algorithm is developed by using the memory forgetting concept. The new TDMP LDPC decoder can further reduce 50% memory requirement.