針對加速電路模擬之區塊層級休眠特性研究

Abstract

由於深次微米時代的來臨，未來數位電路的行為可能必須以混合模式來表示，因此在先進的VLSI設計流程內，電晶體層級的模擬將是不可或缺的一環。然而使用SPICE來模擬電路卻是一件很費時的工作，但在實際上，特別是對數位電路而言，常常有很大的一部分是屬於休眠不動的，藉著利用這樣的特性，我們可以節省相當多的運算時間如果只考慮電路中活動的部分。在這篇論文裡，我們提出了一個可以依照來自於基本輸入端的訊號而自動偵測子電路狀態的演算法，因為沒有利用任何的外插公式，我們可以有效率且正確的判斷每一個子電路是否是處於休眠狀態中，因此可以提供相當穩定的模擬品質由。除此之外，由於我們對於電路分割的特別討論，這會使得一個利用區塊層級休眠特性的電路模擬器達到不錯的休眠使用比率。同時，我們還特別針對模擬時的主要動作LOAD以及SOLVE個別的設計了新的元件旁路機制與矩正解法器，好讓他們也能有效的使用到電路休眠的好處。藉著把上述所有的方法集合起來，我們即可於加速與精確度之間達成良好的平衡點，而且實驗的部分也證明的我們的做法確實是可行的。

Due to the coming of deep submicron era, behaviors of digital designs may have to be modeled as mixed signal ones. Transistor-level simulation will become indispensable in modern VLSI design flow. However, circuit simulation with SPICE is too costly and time consuming. But in practice, especially in digital circuits, there is a large portion of circuit latent at any given time. By exploiting latency, only the active portions of the circuit equations have to be formulated and solved. This will reduce the computation time significantly. In this thesis, we propose an algorithm which can automatically detect a subcircuit's state, latent or active, efficiently and accurately by making use of signals from primary inputs rather than using extrapolation. Thus we can provide stable simulation quality. In addition, we can make a block-level latency usage simulator to accomplish high exploitation rate by using circuit partitioning technique. We also provide a new device-bypass mechanism and a novel matrix solver to fully take advantage of circuit's latency in LOAD and SOLVE during simulation respectively. By combining all mentioned features, our simulator can achieve a good compromise between speed-up and accuracy, and experimental results show that our approach is applicable to real designs