低溫形成複晶矽薄膜電晶體之研製與應用

Abstract

利用複晶矽薄膜電晶體製作畫素元件及周邊驅動電路已成為發展主動式平面顯示器的重要技術。本論文的研究在於深入探討有關複晶矽薄膜電晶體的製程與應用。 首先，吾人探討的是低溫製作複晶矽薄膜電晶體的一種調變製程。所謂調變製程，是將傳統製程中的固相結晶製程步驟刪除，而在源╱汲極離子佈植後以單一的退火步驟來同時完成固相結晶及離子佈植退火之目的。以調變製程製作複晶矽薄膜電晶體不僅可以縮短製程時間而且元件的特性也可以得到改善。元件特性改善的主要原因是因為源╱汲極的離子佈植區和元件通道區的結晶速率不一致，導致源╱汲極區的晶粒向通道區側向成長而造成通道區具有較大的複晶矽晶粒。以氨氣（NH3）電漿處理分別鈍化調變製程所製作的元件和傳統製程所製作的元件所獲得的不同鈍化效率可以用來驗證調變製程所製作元件之通道複晶矽確實具有較大的晶粒。 以準分子雷射退火處理形成複晶矽導通層而製作之複晶矽薄膜電晶體具有較佳的元件特性。吾人首先深入瞭解準分子雷射退火處理形成複晶矽導通層之機制，並且探討複晶矽表面形態與雷射退火製作之元件的特性和可靠度之間的關聯性。雷射退火處理所形成之複晶矽膜的主要特徵為具有非常粗糙的表面形態，此乃因晶粒邊界的突起所造成。該表面形態的粗糙度隨雷射退火能量的增加而增加，因而導致元件漏電流及可靠度之劣化，其機制主要是由於複晶矽膜（即複晶矽通道）的電阻因結晶性的增加而降低，以及晶粒邊界突起變大導致區域電場之增強所致。此外，增強的區域電場亦將導致元件可靠度的劣化。不過，吾人發現氨氣電漿鈍化處理可以有效的改善雷射結晶複晶矽薄膜電晶體的性能及可靠度。 本論文研究也發現笑氣（N2O）電漿處理具有提昇雷射結晶複晶矽薄膜電晶體元件性能的效果。笑氣電漿處理係在低溫閘極氧化層沉積之後實施者。笑氣電漿產生的氮及氧的活性離子，留存在元件內部產生鈍化效應，使得閘極氧化層和複晶矽通道間的介面變得較為平坦，並且改善閘極氧化層的品質，減少閘極氧化層、複晶矽通道、以及兩者間介面處的缺陷數量，導致元件性能的明顯改善。再者，笑氣電漿處理也顯著提昇元件的可靠度。 在實施雷射退火結晶之前，以離子佈植法將氟（Fluorine）離子植入準備結晶化的非晶矽薄膜內，也具有改善複晶矽薄膜電晶體元件性能的功效。運用該項技術研製所得之雷射結晶複晶矽薄膜電晶體具有極低的漏電流(0.26 pA/μm)及相當高的開關電流比(108)，而且元件的可靠度也獲得顯著的改善。吾人認為上述的元件性能改善與複晶矽導通層和緩衝氧化層間的介面應力釋放以及一些位於複晶矽通道層內部及複晶矽通道層和閘極氧化層間的介面之缺陷數量的減少具有相當大的關聯性。 除了以上有關以固相結晶及雷射結晶技術研製複晶矽薄膜電晶體之外，本論文研究也對一種組合固相結晶及雷射結晶的二階段結晶技術作深入的探討。該二階段結晶技術乃是先以雷射結晶方式形成一極薄的成核晶種層，再以較短時間的固相結晶方式成長出具有低缺陷密度之結晶晶粒的複晶矽膜。以二階段結晶技術製作之複晶矽薄膜電晶體不僅具有較佳的元件特性，而且製程所需時間比傳統的固相結晶製程大幅縮短，並且元件特性的均勻度不僅不亞於傳統的固相結晶製程所得者，而且遠比雷射結晶製程所得元件的特性均勻度為佳。 最後，為了驗證本論文所製作之複晶矽薄膜電晶體的實用性，吾人將第五章所製作出來的元件當作像素電路的主動元件，應用在1.9吋、120x160x3解析度的主動式有機發光二極體顯示器上做一模擬設計，其中元件的電路參數係以目前複晶矽薄膜電晶體的商用模型軟體來加以淬取。本項顯示器之像素電路設計的關鍵點在於如何產生一均勻明亮度的顯示標的。因此在設計時，吾人採用具有最佳製程控制的雙電晶體結構作為像素電路的單元。從電路軟體模擬的結果得知，作為像素電路主動元件的複晶矽薄膜電晶體不僅可以對有機發光二極體做快速充電，而且可讓儲存電容具有很長的電荷持有時間。模擬結果證實第五章所製作之複晶矽薄膜電晶體具有實際運用於主動式有機發光二極體顯示器之像素電路的性能。 吾人相信，由於低溫形成複晶矽薄膜電晶體的製程技術與應用的快速發展，必將在不久的將來使整個主動式平面顯示器的產業及技術產生結構性的巨大轉變。

The use of low-temperature processed polycrystalline silicon thin-film transistors (LTP poly-Si TFTs) as pixel active elements and in peripheral driver circuits has been an important issue in the development of active-matrix flat panel displays (AMFPDs). This thesis studies a number of processing techniques for the high performance LTP poly-Si TFTs and the application of the devices as pixel active elements in a practical AMFPDs. Firstly, a modulated process (MP) for the fabrication of LTP poly-Si TFTs is explored. In the modulated process, the processing step of solid phase crystallization (SPC) is omitted, such that the SPC and implant annealing are conducted simultaneously after the source/drain implantation. In this way, the process time is substantially shortened and the device performance is significantly improved. The improvement of device performance is attributed to the larger poly-Si grain in the channel region, which can be verified by the different NH3-plasma passivation efficiency for the MP and the control samples. Polycrystalline silicon obtained from amorphous silicon (a-Si) via excimer laser annealed (ELA) crystallization possesses structural grains of super quality with very few in-grain defects. Thus, one of the major studies of this thesis is to explore the ELA poly-Si TFTs. The main feature of ELA poly-Si films is the protrusion at grain boundaries that makes the film surface appearing very rough. The surface roughness increases with increasing laser energy density (LED), and the resultant roughness of the gate-oxide/poly-Si interface causes degradation of off-current and reliability for the ELA poly-Si TFTs. This degradation is attributed to the lowered channel resistance due to the increase in crystallinity of the poly-Si layer and the enhancement of local electric field arising from the protrusion at the grain boundaries. Passivation of gate oxide/poly-Si channel by NH3-plasma treatment is found to be favorable in improving the performance and reliability of the ELA poly-Si TFTs. The N2O-plasma treatment on ELA poly-Si TFTs is found to result in significant improvement in the device performance. The N2O-plasma treatment is conducted following the deposition of the low-temperature gate-oxide, resulting in improved gate-oxide quality, smoothed gate-oxide/poly-Si interface, and reduced trap states at the interface and in the poly-Si channel region because of the passivation reaction of the N2O-plasma generated nitrogen and oxygen radicals. Moreover, the N2O-plasma treatment also improves the device stability with respect to the dc voltage stress. The incorporation of fluorine atoms using ion implantation into α-Si films before the ELA crystallization presents another technique for the performance improvement of ELA poly-Si TFTs. We achieve, with fluorine ion implantation, high performance ELA poly-Si TFTs with a very low off-current of about 0.26 pA/μm and a very high ON/OFF current ratio of about 108. Moreover, this technique also greatly improves the reliability of the ELA poly-Si TFTs with respect to the hot-carrier stress. This improvement of device performance is attributed to the relaxation of mechanical stress at the poly-Si/buffer-oxide interface and the passivation of trap-states in the poly-Si channel region and at the gate-oxide/poly-Si interface. Since ELA poly-Si TFTs tend to suffer from poor uniformity of device characteristics, a novel two-step annealing (NTSA) technique for the fabrication of LTP poly-Si TFTs is developed in this thesis study. The NTSA scheme is characterized by the combination of an excimer laser induced formation of nucleation centers and a short-time low temperature furnace annealing (about 6 hours at 600℃), creating clear crystalline grains with very few in-grain defects. The LTP poly-Si TFTs fabricated with an NTSA poy-Si film not only exhibit a better performance but also have a significantly shortened crystallization time as compared to those fabricated using the conventional SPC (about 20 hrs or longer at 600℃). The uniformity of device characteristics for the devices using the NTSA scheme is superior to that using the ELA scheme and is comparable to that using the SPC scheme. Finally, to demonstrate the practicability of the ELA poly-Si TFTs fabricated in this thesis, the devices explored in chapter 5 are used as active elements in the pixel circuit for a simulation design of a 1.9-inch active-matrix organic light emitting diode displays (AMOLEDs) with a resolution of 120x160x3 using an H-SPICE circuit simulator. The circuit parameters of the poly-Si TFTs are extracted using the RPI poly-Si TFT model. The main concerning issue of the AMOLEDs pixel design is the uniform brightness throughout the display, and the preferred design approach is the two TFTs per pixel structure in conjunction with a good process control. The results of simulation indicate that the ELA poly-Si TFTs fabricated in chapter 5 are capable of acting as active elements in the AMOLEDs application.