超大型級晶片可靠度分析及主動元件安裝於金氧半電晶體之輸出入墊片下之研究與製程技術智財自動化之設計

Abstract

本論文呈現以下幾點創見性的研究: 特殊設計一超大型級之測試載具晶片, 內含有一連串高敏感度之測試結構, 用以偵測超大型晶片在不同製程技術製造下之可靠度分析, 並提出一新的應力模組理論, 來估算晶片故障分布與故障機構模式。 結果呈現超大型晶片故障之韋伯 (Weibull) 統計分布與晶片幾何大小, 封裝材料相關, 其百分之 63 故障數隨晶片面積與封裝材料本質應力大小改變。 由韋伯統計分布曲線淬取出之行為參數值 β 約在 2, 顯示出晶片故障應是製程缺陷所造成. 並由理論計算得知在鋁製程之晶片故障機構為脆性斷裂模式。 然而使用大馬士革之銅金屬製程所產之晶片比鋁製程之晶片有更高的可靠度。 深入研究, 我們認為大馬士革銅金屬製程具有低製程缺陷, 最佳的平坦度及抗應力, 且銅金屬比鋁金屬有更好的延展性與較低阻抗。 因此, 對超大型級晶片之製造銅金屬製程是較佳的選擇. 此外, 隨著積體電路設計日趨複雜化與高密度化, 使積體電路晶片尺寸亦隨之增大, 尤其是以系統單片為主流時代的來臨。 因此, 本論文提出一可縮減晶片面積大小之可行性方法, 將元件置於輸出入墊片下方。 首先, 由應力分析模擬和針壓實驗, 我們找到一最佳抗應力緩衝層: 1.2 微米厚度之鋁金屬薄膜鍍於輸出入墊片上方。 再將靜電放電保護元件及環狀振盪電路置於輸出入墊片下方。 於是, 在傳輸線脈衝高壓測試下, 輸出入墊片下之靜電放電保護元件的二次崩潰電壓和電流曲線仍具優秀的特性。 而在直流與交流實驗測試下, 輸出入墊片下之環狀振盪電路的傳播延遲時間仍然保留在大約 20 微微秒左右。 這輸出入墊片下之靜電放電保與環狀振盪電路特性並沒有受到外力影響。 證實了元件置於輸出入墊片下方的可行性。 運用此一方法將可降低傳統晶片面積的大小。 半導體矽製程技術遵循摩爾定律, 積極地跨出新一代製程技術, 驅動著積體電路往更高速更高密度且功能更複雜的設計。 隨著矽製程技術達到它的物理極限, 人們正開發各種不同的方法與材料以延長它的生命周期, 包括低介電材料, 銅金屬導線製程與絕緣矽。 而這些新技術和新材料須利用以前所使用過的測試結構來瞭解新技術和新材料的特性。 本論文最先提出稱此測試結構為矽製程技術智財。 矽製程技術智財在製程技術佔有極重要的地位, 往往設計錯誤的矽製程技術智財無法將新技術和新材料關鍵參數萃取出, 造成技術開發的延遲與成本增加。 為此, 本論文發展一新程式語言用以設計系統化之矽製程技術智財。 用新程式語言設計矽製程技術智財在本論文中證實具有跨世代跨晶圓製造廠區且自動化之特性, 滿足次微米, 深次微米以及奈米和其下次代以下之矽製程技術開發之需求。

This dissertation presents the modeling and characterization of reliability of the large-die-size VLSI-level chip in two different back-end CMOS technologies, generic 0.18 $\mu m$ six-level AlCu-hydrosilsesquioxane (HSQ) and specific dual-damascene Cu-fluorinated SiO$_{2}$ (FSG). The impacts of area and location of a chip, the material from which it is encapsulated, the geometry of the test structures, accelerated stressing operations on the reliability testing are investigated. On the other hand, a novel method, active devices placed under CMOS I/O pads, has been stringently proven to be feasible in this dissertation. Additionally, new-developed programming language, technology independent description language (TIDL), relates to a layout method for autonomous design of technology intellectual property. Using a special-designed large-die-size test chip with a variety of the sensitive top two metal test structures, The shape parameter in AlCu/HSQ back-end technology is the same for temperature cycling (TC) and thermal shock (TS) reliability testing induced stresses. The same brittle fracture failure mechanism occurs in each case since the Paris Law exponent lies in the range for brittle fracture. The failures induced by both TC and TS operations are independent of the number of sites in the chip corner. The area of the chip and the geometry of the test structure can affect the magnitude of the intrinsic stress. Such intrinsic stress directly influences the stress, changing the $N_{63}$ of the data lines in the Weibull plot. Additionally, CTE mismatches induced by interactions between compound materials and the silicon chip also alter the magnitude of the intrinsic stress, impacting S to result in the different $N_{63}$ of the data lines in the Weibull plot. Finally, test chips fabricated in generic 0.18 $\mu m$ six-level AlCu/HSQ technology and specific dual damascene Cu/FSG technology just for top two-level metal differ significantly in the failure rate during tests of the reliability of the chip assembly. The results show that the mechanical and electrical performance of the packaged test chip depends strongly on the back-end process, which thus greatly impacts the failure distribution and the failure mechanism. This thesis examines active devices, including electrostatic discharge protection (ESD) device and ring-oscillator circuit, under CMOS I/O pads. The 1.2 $\mu m$ aluminum metal film is deposited on the 1.0 $\mu m$ top most copper metal layer for an effective bonding mechanism stressing buffer layer to protect active devices under CMOS I/O pads. The high current I-V curve measured in the second breakdown trigger point (V$_{t2}$, I$_{t2}$) of ESD protection devices under various metal level stack structures, shows that (i) I$_{t2}$ depends very weakly on the number of metal levels used, as expected given specific junction power dissipation criteria; and (ii) V$_{t2}$ increases with the number of metal level stacks of I/O pads because of increased dynamic impedance due to the presence of more metal levels, as clarified by a simple $RC$ model. Moreover, no noticeable degradation in the speed of the ring-oscillator circuit, as measured for a variety of test structures subjected to bonding mechanical stress, thermal stress by temperature cycling and $dc$ electrical stress by transmission line pulse, as well as $ac$ electrical stress by capacitive-coupling experiments. Accordingly, active devices under CMOS I/O pads is independent of bonding pad metal level structures. The programming approach using a new-developed syntax, technology independence description language, for autonomous design of technology intellectual property (TIP) in submicron, deep submicron, ultra deep submicron, nanoscale and beyond CMOS process technologies has been realized in this dissertation. Design of TIPs based on TIDL syntax models variables of TIPs in a descriptive approach, independent of technology and design rules change, and parameterizes TIP creation so that TIDL-programmed TIPs can be built in the previous well-proven technology knowledge, parameters of device simulation profile, and embedded new technology know-how, process constraints and checking ranges, physical design rules and reliability description. Such TIPs satisfy semiconductor technology development and manufacturing with autonomously instant revisability, portability, reusability, compatibility, and standardizability, and alleviate the error-prone, time-consuming and expensive development of TIPs created by a free-hand layout.