標題: ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
作者: Ker, MD
Lin, KH
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: electrostatic discharge (ESD);input/output (I/O) cell;silicon controlled rectifier (SCR);power-rail ESD clamp device
公開日期: 1-十一月-2005
摘要: This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail ESD clamp device in a 130-nm CMOS process. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. Experimental results have verified that the human-body-model (HBM) ESD level of this new proposed I/O cells can be greater than 5 kV in a 130-nm fully salicided CMOS process. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of the I/O cell.
URI: http://dx.doi.org/10.1109/JSSC.2005.857349
http://hdl.handle.net/11536/13096
ISSN: 0018-9200
DOI: 10.1109/JSSC.2005.857349
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 40
Issue: 11
起始頁: 2329
結束頁: 2338
顯示於類別:期刊論文


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