完全自動對準之高功率金氧半場效應電晶體

Abstract

完全自動對準之高功率金氧半場效應電晶體 研究生:顏天才 指導教授:崔秉鉞 國立交通大學 電子工程學系 電子研究所碩士班 摘要 近年來雖然有各種不同的自動對準技術的提出以提高溝槽式金氧半場效功率元件密度，而且更有人藉由先進蝕刻技術將元件寬度縮小以提高元件密度。但這些製程在技術上仍舊存有許多潛在的缺點，且採用先進的製程技術，製程難度及成本也相對提高。 前人利用精密的蝕刻製程，以及0.2μm的溝槽寬度，雖然能將元件寬度縮小至1μm而且再藉由減少磊晶層與基板厚度能將特徵導通電阻降低至0.1mΩ-cm2，但因為必須仰賴精密的蝕刻技術，會使製程成本提高，窄溝槽底部尖端電場變大，會使閘氧化層可靠度劣化，近似飽和電流降低。數值模擬顯示，在同樣的元件寬度下，溝槽寬度愈小，近似飽和現象愈嚴重，如果能夠在不縮小溝槽寬度的情況下，縮小元件寬度，將是最理想的作法。因此與現今所提出的先進製程技術相比，完全自動對準技術反而具有更大的競爭性。 在本論文中，我們成功開發一種新穎的全自動對準溝槽式金氧半場效功率電晶體製程技術，即斜角度源極離子植入自動對準技術再配合接觸窗完全回蝕刻技術，可以在0.6μm的製程技術下，不需要精密的蝕刻技術縮小溝槽寬度，即可大幅提高元件密度，並減少源極與場氧化層光罩以降低製程成本。採用完全自動對準技術實際製作結果顯示，當元件寬度縮小至1.5μm，元件密度達到286Mcell/in2，特徵導通電阻在閘極電壓10V下為0.2mΩ-cm2，崩潰電壓為36V。當元件寬度縮小至1.2μm，特徵導通電阻更可降低至0.18mΩ-cm2，雖然相隣的源極接面結合導致崩潰電壓只有17V，但只要降低源極接面深度即可解決。若進一步將汲極飄移區的磊晶厚度減薄，並將矽基板厚度降低至標準封裝厚度，估計特徵導通電阻可以降低至0.14 mΩ-cm2以下。 簡言之，本論文發展出新穎的全自動對準技術，可以在相同的0.6μm製程技術下，減少兩層光罩，將元件密度提高。若再將磊晶厚度，矽基板厚度減薄以及縮小元件寬度與溝槽深度，其特徵阻抗也有降低至0.2μm溝槽寬度所能達到的低值，相當於三個製程世代的技術水準差距，極具競爭力。

A Fully Self-Aligned Power MOSFET Student:Tian-Choy Gan Advisor: Bing-Yue Tsui Department of Electronics Engineering Institute of Electronics National Chiao Tung University ABSTRACT Recently, many different self-aligned fabrication methods have been proposed to increase trench gate power MOSFTEs cell density and advance etching technique has been used to reduce cell pitch and increase packing density. However, these fabrication methods still have many latent problems. By using advance technology , the process steps will become more difficult and process cost will be increased. Using advance etching technique and 0.2μm trench width, somebody can reduce cell pitch to 1μm and improve specific on resistance to 0.1 mΩ-cm2 by reducing the thickness of epitaxy layer and substrate layer. There are still some problems which will increase cost-effective and trench bottom electric field, degrade gate oxide quality and decrease quasi-saturation current. According to numerical simulation results, in the same cell pitch, quasi-saturation behavior will become serious with the decrease of trench width. Using fully self-aligned technique can shrink cell pitch without changing trench width. Therefore, comparing with advance process technique, fully self-aligned technique is more competitive. In this dissertation, we develop a novel fully self-aligned trench gate power MOSFETs technique successfully which employs tilt angle source implant self-aligned technique and fully contact recess technique. Using 0.6μm process technology, we can use this fully self-aligned process to obtain a remarkably increased high density trench gate power MOSFET. Besides, the masking steps for the active region and source region can be eliminated and cost-effective also can be decreased. Using fully self-aligned technique , cell density can achieve 286Mcell/in2 when the cell pitch is 1.5μm . Also the specific on-resistance of 0.2 mΩ-cm2 at a gate voltage 10V with a blocking voltage of 36V is obtained. The specific on-resistance can be reduced to 0.18 mΩ-cm2 when cell pitch shrinks to 1.2μm. Although the breakdown voltage of device with a pitch of 1.2μm drops to 17V, this problem can be improved by reducing source junction depth. If we reduce the thickness of epitaxy layer and substrate layer further, we will obtain the specific on-resistance smaller than 0.14 mΩ-cm2. In a word, we develop a novel fully self-aligned trench gate power MOSFET technique which can increase cell density and eliminate two mask layers under 0.6μm process technology. If we reduce epitaxy layer thickness, substrate layer thickness trench depth, and cell pitch, using fully self-aligned technique will obtain the same specific on-resistance that can be obtained with advance technique. The difference of this two processes is equivalent to that of three generation technology. Therefore, fully self-aligned technique is more competitive.