一個應用於直接序列展頻無線區域網路使用差異解碼技術之基頻處理器

Abstract

採用直接序列展頻調變的標準包含802.11, 802.11b以及802.11g等無線區域網路系統。無線通訊使用空氣當作介質，比有線通訊多了更多的不確定性，因此，無線通訊系統的封包裡一般都會定義preamble欄位作為接收端同步之用。 在本論文中，我們想利用經過Barker碼展頻過的preamble欄位來消除通道中的非理想效應，例如高斯雜訊、載波頻率誤差、載波相位誤差、以及取樣頻脈誤差等等。於是，我們提出了應用差異解碼概念的符號(symbol)同步、頻率同步、相位同步、以及時間同步等演算法來處理這些非理想效應。 我們所提出的演算法中，接收器只需要利用PLCP中的preamble欄位就可以得知通道的重要參數，而不須MPDU的任何協助，此法可減低互補編碼(CCK)解碼器的成本，其成本佔了整個收發器的大部分。此法更對802.11g有助益，因為802.11g中有CCK-OFDM模式，也就是Barker碼展頻的PLCP接上正交多工分頻(OFDM)的MPDU。 為了瞭解整個系統，我們使用Matlab建立了系統模擬平台。我們可以觀察系統中任一訊號的波形，並且可以得知通道中的非理想效應對整個系統或某些訊號有何影響。此平台更可以用來驗證我們所提出的同步演算法，本論文中也放了一些模擬結果圖。 我們也討論了系統關鍵零組件的架構、實現方法以及設計成本。 最後，點出了未完成的部分和一些構想，可作為未來修改的參考。

Direct sequence spread spectrum (DSSS) technique is used in IEEE 802.11, 802.11b and 802.11g wireless LAN systems. Unlike the wire channel, wireless communication uses radio as its medium and has more uncertainty with it. Therefore, WLAN frame format generally contains preamble field for synchronization. We would like to use the Barker spread preamble field to eliminate non-ideal channel effects including Additive White Gaussian Noise (AWGN), carrier frequency offset (CFO), carrier phase offset (CPO), and sampling clock offset. Therefore, symbol synchronization, frequency synchronization, phase synchronization and timing synchronization algorithms based on differential decoding concept were proposed. With our algorithms, the receiver would extract all the channel parameters only with the PLCP preambles and does not need any help from the MPDU which would reduce the CCK demodulator cost where dominates the cost of the system. These algorithms would benefit the IEEE 802.11g system which has the CCK-OFDM mode, the frame consists of the Barker PLCP and OFDM MPDU. To get familiar with IEEE standards, simulation platforms were set up with Matlab mathematical software which let us have a chance to probe signals in every place inside the system and visual view of the channel effects including CFO, AWGN, clock drift and even multipath. With this platform, our algorithms could be verified. Some simulation results were shown in this thesis. Architectures of key components were discussed and gate counts of which were listed as well.