針對管線化快速傅利葉轉換處理器的字元長度最佳化之研究

Abstract

快速傅利葉轉換處理器廣泛用於現今影像處理、訊號處理以及通訊系統之中，但是到目前為止還有很多研究進行中以改善其效能。再者，由於系統設計時程的壓力，如何使用設計自動化的方式將快速傅利葉轉換處理器設計時程降低成為一個重要的課題。另外，由於硬體中有效字元長度的影響，量化誤差的選擇在系統設計上也是一項精確度與硬體資源消耗的取捨。因此如何在一定的量化誤差之下盡量減少硬體資源也是一個值得探討的問題。在本篇論文中，我們提出了一個方法，針對了管線化快速傅利葉處理器每級架構規律的特性，試著自動化快速傅利葉處理器的設計流程。利用系統設計者所提供的快速傅利葉處理器點數、訊號對量化雜訊比(SQNR)和處理器速度限制，我們可以藉著調整每級之字元長度，而對特定的管線化快速傅利葉處理器的面積或功率作最佳化。為了減少使用者的設計時程，在我們提出的流程中，自動產生一個擁有週期準確度可模擬的模型，提供設計者方便靈活的模擬環境。實驗結果顯示，此套流程可以減少管線化快速傅利葉處理器的面積或功率消耗並且增加系統設計上的效率。

Despite the wide use of Fast Fourier Transform (FFT) processors in modern communication system, image and signal processing, much research is still undertaken to improve its performance. Because of the time pressure of system design, it is important to reduce design time of FFT processors through design automation. Furthermore, subject to the effect of finite wordlength in hardware, a trade-off between precision and hardware resource has to be made. Accordingly, it is a key issue to maximize the precision at the minimal cost of hardware complexity. This thesis presents a solution to automate the design flow for pipelined FFT processors that are characterized by the regularity in each stage. We can adjust the wordlength in each stage to obtain the optimization of the area or the power for specified pipelined FFT processors by using the constraints of point of FFT, signal-to-quantization-noise ratio (SQNR), and speed of processors. To decrease the design time, our flow is capable of generating automatically a timing accuracy model which can be simulated. This feature provides designers a flexible simulation environment. The experimental results indicate that this flow can reduce the area or the power of pipelined FFT processors and improve the efficiency in system design.