經由混合方法進行管線化快速傅利葉轉換處理器的字元長度最佳化之研究

Abstract

快速傅利葉轉換處理器是許多通訊系統中的關鍵元件，利用快速傅利葉轉換處理器的設計自動化，可減輕系統設計的時程壓力。在設計管線化快速傅利葉轉換處理器時，處理級(Process Element)的字元長度是重要的參數。在本篇論文中，我們提出關於管線化快速傅利葉轉換處理器每一級的字元長度對訊號對量化雜訊比(SQNR)的統計學模型。更進一步地，提出透過混合使用統計與模擬誤差分析的管線化快速傅利葉轉換處理器字元長度的最佳化流程。在系統設計者所提供的快速傅利葉處理器點數、訊號對量化雜訊比和處理器速度限制條件下，本方法可於數秒內自動地產生一組最佳化的字元長度參數。實驗的結果顯示，此快速的最佳化流程可縮小8192點管線化快速傅利葉轉換處理器面積達24%。

The Fast Fourier Transform (FFT) processor is a key component in many communication systems. To reduce design time of FFT processors through design automation is to reduce the time pressure of system designers. When implementing a pipelined FFT processor the wordlength is of great importance. This thesis describes a statistical error model of pipelined FFT processors that calculates the signal to quantization noise ratio (SQNR) with wordlength of each process element (PE) stage. Furthermore, to speed up the design of specified FFT processor, a hybrid optimization method with statistical and simulation-based error analysis is presented. Under constraints of the number of FFT points, SQNR, and required processors speed, the optimized wordlength set for each PE stage can be generated within several seconds. The experimental results designate that this speedy flow can reduce 24% area of 8192-point pipelined FFT processors.