以靜態機率模型分析為基礎之應用於快速傅利葉轉換處理器設計的精度最佳化技術

Abstract

正交頻分多工系統被廣泛的使用於現今的設計，過去幾十年間可以找到許多關於正交頻分多工計算核心的快速傅利葉轉換處理器的研究資料。這篇論文描述一個應用於正交頻分多工系統的計算核心的快速傅利葉轉換處理器設計的精度最佳化流程，藉由決定每一級的尺規行為來得到最佳化的訊號對量化雜訊比。此方法利用機率分佈來建立每一級輸出信號的靜態行為模型。由無條件捨去法以及飽和算法的雜訊可以因此被分析，而做出小數點位置的決定。我們提出的這種方法不但不用很花費時間的模擬分析，而可以在很短的時間內，固定每一級的數字格式並得到最佳化的訊號對量化雜訊比。這種最佳化流程可以處理不同的快速傅利葉轉換點數、快速傅利葉轉換演算法、字元長度以及輸入的機率分佈。實驗結果顯示我們的方法可以在8192點、以2為基數的快速傅利葉轉換處理器中，跟傳統的靜態尺規化分析方法比較，節省3位元的字元長度，而不增加任何硬體複雜度。精度更是非常接近動態尺規化方法。

As OFDM-based systems are widely adopted in today’s designs, many literatures of FFT processors, the arithmetic kernel of OFDM-based systems, can be found in the past decades. For a high performance FFT processor, many parameters should be decided carefully. In this thesis, we proposed a precision optimization flow to decide the scaling behavior at each stage with optimized output SQNR for FFT processor. The methodology utilizes the probability distribution to model the statistical behavior of the output at each stage. The noise from truncation and saturation arithmetic can be further analyzed to make the scaling decision. Without time-consuming and pattern-dependent simulations, the proposed method fixes the number format at each stage in a short time that gives optimized SQNR. The optimization flow has ability to handle different FFT sizes, FFT algorithms, wordlengths, and distributions of input signals. Experimental results designate that about 3 bits wordlength can be saved in 8K-point, radix-2 FFT processor, with no increasing in hardware complexity compared to traditional static scaling method. Furthermore, the precision is very close to the dynamic scaling method.