5-GHz CMOS 雙增益模式之IEEE 802.11a 前端接收器設計

Abstract

這篇論文中完成一個802.11a雙模直接載頻高頻無線接收器，電路製作平台環境採用UMC 0.18μm 1P6M製程、智森高頻元件模組、矽品QFN系列封裝、與FR-4印刷電路板。實作電路內容包含一個低雜訊放大器、降頻混波器、高通濾波器、與一個基頻放大器。量測結果顯示，在高增益和低增益模式下的電路增益分別為27.4dB與14.3dB，三階交調點(IIP3)分別為-12.8dBm與+4.5dBm。二階交調點(IIP2)為-13.5dBm，雜訊指數為8.5dB。

In this thesis, a dual gain mode direct-conversion receiver front-end under 802.11a specification is designed and implemented by UMC 0.18μm 1P6M process. Giga-solution RF component models, SPIL QFN series package, and FR-4 printed-circuit-board are adopted for the implementation and assembly. The front-end implementation includes a LNA, a mixer, a high pass filter, and a baseband amplifier. The measurement result indicates the voltage gain to be 27.4dB and 14.3dB under high and low gain mode individually, and IIP3 is measured as -12.8dBm and +4.5dBm. IIP2 is measured as -13.5dBm, and noise figure is 8.5dB.