完整後設資料紀錄
DC 欄位語言
dc.contributor.author唐偉烝en_US
dc.contributor.authorWei-Cheng Tangen_US
dc.contributor.author溫瓌岸en_US
dc.date.accessioned2014-12-12T02:30:46Z-
dc.date.available2014-12-12T02:30:46Z-
dc.date.issued2002en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT910428122en_US
dc.identifier.urihttp://hdl.handle.net/11536/70453-
dc.description.abstract這篇論文中完成一個802.11a雙模直接載頻高頻無線接收器,電路製作平台環境採用UMC 0.18μm 1P6M製程、智森高頻元件模組、矽品QFN系列封裝、與FR-4印刷電路板。實作電路內容包含一個低雜訊放大器、降頻混波器、高通濾波器、與一個基頻放大器。量測結果顯示,在高增益和低增益模式下的電路增益分別為27.4dB與14.3dB,三階交調點(IIP3)分別為-12.8dBm與+4.5dBm。二階交調點(IIP2)為-13.5dBm,雜訊指數為8.5dB。zh_TW
dc.description.abstractIn this thesis, a dual gain mode direct-conversion receiver front-end under 802.11a specification is designed and implemented by UMC 0.18μm 1P6M process. Giga-solution RF component models, SPIL QFN series package, and FR-4 printed-circuit-board are adopted for the implementation and assembly. The front-end implementation includes a LNA, a mixer, a high pass filter, and a baseband amplifier. The measurement result indicates the voltage gain to be 27.4dB and 14.3dB under high and low gain mode individually, and IIP3 is measured as -12.8dBm and +4.5dBm. IIP2 is measured as -13.5dBm, and noise figure is 8.5dB.en_US
dc.language.isoen_USen_US
dc.subject5GHzzh_TW
dc.subject接收器zh_TW
dc.subject802.11azh_TW
dc.subjectRFen_US
dc.subjectCMOSen_US
dc.subject5-GHzen_US
dc.subject5GHzen_US
dc.subjectReceiveren_US
dc.subjectRxen_US
dc.subject802.11aen_US
dc.subjectDirect Conversionen_US
dc.title5-GHz CMOS 雙增益模式之IEEE 802.11a 前端接收器設計zh_TW
dc.title5-GHz CMOS Dual Gain Mode Receiver Front End Design for IEEE 802.11aen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
顯示於類別:畢業論文