高速應用之傳輸電路設計

Abstract

隨著處理器運算的速度越來越快，但是在許多的應用上，真正效能的頻頸卻是在晶片間或是PCB板間資料傳輸的頻寬上。另一方面，接墊尺寸縮小的速度遠遠比不上製程演進的速度。所以，最好的解決方法就是使用高速介面傳輸電路，利用有限個數的接墊來傳送大量的資料。 許多的數位系統使用完整振幅的訊號來傳送資料，這在高速和低功率方面是不適合的。而若要達到高速且低功率的要求，則差動低電壓振幅模式來傳送訊號是較佳的選擇。 本論文的研究有兩部份，第一部份是2 Gbps訊號傳送機的電路設計，它是利用0.25um CMOS的製程來實現，且操作在2.5V的電壓下，收發速度能達到2 Giga-bit/s。 論文的第二部份則是正向射極耦合邏輯（PECL）傳送機電路設計，它是利用操作在3.3V 0.35um CMOS 的製程來實現，與ECL 100K的邏輯電路相容，該電路之高電壓準位為2.35V,低電壓準位為1.58V，其傳送速度能達到數百mega-bit/s以上。

The operation speed of processor becomes more and more fast, but for many application systems, the major performance limit factor is the interconnection bandwidth between chips or boards. In the other hand, as technology continues to scale down, the size of pad scale more slowly. Therefore, using high speed I/O interface circuit in limited pads to transmit huge data is the best solution. Many digital systems use full-swing signaling method that is unsuited for high speed and low power. For taking high speed and low power into account, the transceiver uses differential small voltage swing to transmit signal. The researches of this topic have two projects. The first one, Transmitter for 2 Gbps signaling is implemented by 2.5V 0.25μm CMOS process and the data rate is up to 2 giga-bit per second. The second one, Positive Emitter Couple Logic (PECL) transmitter is implemented by 3.3V 0.35μm CMOS process, and the data rate is up to hundreds mega-bit per second.