可變長度快速傅立葉轉換處理器之設計

Abstract

為了設計一個具彈性而有效率的可變長度快速傅立葉轉換處理器以適用於多種正交分頻多工的通訊系統，本論文由演算法至架構層次研究各種關於快速傅立葉轉換的技術。同時，我們也分析了各種正交分頻多工通訊系統對快速傅立葉轉換處理器的效能要求。本論文提出了數種控制器設計，包含資料位址產生器、係數位址產生器以及轉置因子產生器，用以實現低功率、低成本的可變長度快速傅立葉轉換處理器，本論文將會呈現整合以上新設計所實作的一個設計範例。最後，本論文提出一個可適用於802.11a、802.16a、數位音訊廣播、數位影像廣播、以及超高速數位用戶迴路等通信標準的可變長度快速傅立業轉換處理器的架構設計。

In order to design a flexible and efficient variable-length FFT processor module suitable for various OFDM communication systems, the thesis studies various design techniques from algorithm level to architecture level. Key issues and consideration for the design of an FFT processor applied to specific OFDM communication systems are also analyzed. The thesis proposes several controller designs that include an improved data address generator, coefficient index generator, and twiddle factor generator, for the realization of a low-power and low cost variable-length FFT processor. Following that, the thesis realized design example that integrates some proposed techniques is presented. Finally, the thesis proposes a variable-length FFT processor architecture, which can suit the needs of all the FFT demodulation operations of 802.11a, 802.16a, DAB, DVB-T, and VDSL.