應用在802.11A接收端與等化器之設計

Abstract

本論文提出一個高精準且低複雜度，應用於IEEE802.11a規格之等化器(Equalizer)，載波頻率偏移補償(Carrier frequency offset compensation)，及取樣時間偏移補償(Sampling clock offset compensation)。 在設計等化器的部分，在每個封包之前的long preambles可用來提供通道響應估計，本論文提出一種可以獲得更精準的通道響應估計方法。在載波頻率偏移補償以及取樣時間偏移補償的部分，除了利用long preambles之外，pilot signals也同時用來幫助我們獲得更精準的估計量。利用這些方法，在輸入的訊號雜訊比 (SNR)為22 dB，追蹤(Tracking)穩定了以後，載波頻率偏移只剩下小於0.1ppm誤差，取樣時間偏移只剩下小於1ppm誤差。硬體實現部分FPGA被用來實現我們的設計。

In the thesis an effective algorithm for equalization, carrier frequency offset compensation, and sampling clock offset compensation for OFDM based wireless LAN specified in 802.11a are proposed. In the design of equalization, two long preamble specified in front of one packet is used to estimate channel response. A new method is proposed to estimate channel response more accurately. Two long preambles and pilot signals are used to estimate the carrier frequency offset and sampling clock offset compensation. With the SNR input equal to 22dB, the residual amount of CFO, SCO is less than 0.1ppm and 1ppm. FPGA is used to implement our design.