具副閘極之多晶矽薄膜電晶體製作與特性研究

Abstract

傳統多晶矽薄膜電晶體的高關閉態電流(Ioff)阻礙了它們在主動矩陣方面的應用。解決此問題的兩個最常用的方法，是淡掺雜汲極(lightly-doped drain, LDD)結構及場感應汲極(field-induced drain, FID)結構。與淡掺雜汲極結構不同的是，場感應汲極結構不只可減低異常的漏電流而且可以保持高的導通電流。在本論文中，我們製造且探討了幾種場感應汲極結構。 首先，我們製作且探討兩種具上副閘極(top sub-gate)的多晶矽薄膜電晶體。在這些元件中，一金屬場導板(metal field-plate)置於覆蓋氧化層(passivation oxide)之上，且此金屬場導板用於在通道偏置區感應出導電接面。從元件模擬的結果得知，場感應汲極元件中的最大電場遠小於傳統的薄膜電晶體的電場。再者，場感應汲極元件中的主通道層區的電子濃度也幾乎與傳統結構相同。實驗結果顯示這些元件可大幅降低存在於傳統自我對準結構中的高漏電流。我們也比較了經不同電漿(NH3 and H2)處理的元件特性。隨著電漿處理時間的增加，多晶矽通道層薄膜的品質可進一步改善，也因此造就了較佳的元件特性。 其次，我們提出一新式具自我對準場感應汲極(Self-Aligned Field-Induced-Drain, SAFID)結構的薄膜電晶體。此新式結構特別之處在於具有一下副閘極且用其上的邊壁間隔造成自我對準場感應汲極以製作有效的場感應汲極長度。與傳統薄膜電晶體不同的是，場感應汲極可分散汲極的高電場並且可以消除類閘極誘導汲極漏電(gate-induced drain leakage-like, GIDL-like)的關閉態漏電流。此下副閘極結構可展現較佳的元件特性。並且，我們也製作且探討另一種具上副閘極的FID結構。此上副閘極結構中，主閘極可自我對準於副閘極。然而，內邊壁之下的高電阻通道區會降低導通特性。此外，我們製作不同覆蓋層的元件來研究製程溫度的影響。實驗及模擬的結果指出覆蓋氧化層的溫度嚴重的影響元件特性，這是由於掺雜的擴散距離所致。由此可見如果製程熱處理溫度太高將會造成高的關閉態漏電流以及較差的開關電流比。 為了解決自我對準場感應汲極結構中製程熱處理溫度的影響，我們提出另一個以光阻定義較長偏置區的元件。此元件的各種特性也一併探討。以此方式製作的n型及p型元件的開關電流比可高達107。元件模擬也顯示此結構可有較低的電場。然而，當通道長度縮小至1□m以下時，關閉態電流會急遽增加。此外，在次臨界電流電壓特性中發現一隆起(hump)現象。經過仔細的分析後發現漏電流與電場強度有關。從結構來看，沿著多晶矽通道層底部表面漏電通道會造成此異常漏電現象。 最後，我們對前面提出的底閘極感應汲/源極的多晶矽薄膜電晶體做NH3及H2的電漿處理來探討其影響。我們的結果顯示此兩種電漿都能改善元件特性，但相較之下NH3電漿不管在關閉態漏電、次臨界擺幅、及開關電流比的改善都比H2電漿來的大。再者，NH3電漿更可有效改進在無電漿處理的短通道元件中所發現的異常次臨界隆起現象。更進一步的分析說明了所有的改善都是由於NH3電漿有效的覆蓋存在於通道層上部及下的陷阱。我們引入兩個漏電機制來解釋短通道元件中的異常漏電流。在此我們也探討通道寬度的影響。實驗數據顯示，窄通道元件可獲較完全的電漿覆蓋，也因此漏電流可以有效降低。另外，未經CMP處理的元件其電特性並無隆起現象，此結果有力的支持我們的結論，那就是CMP處理會造成缺陷產生進而影響元件特性。

The use of conventional poly-Si TFT’s for active matrix applications was hampered by the undesirable large off-state current (Ioff). Two popular strategies are proposed for solving this problem, namely, lightly-doped drain (LDD) and field-induced drain (FID). Unlike the LDD approach, the FID structure not only reduces the anomalous leakage current, but could also maintains a high on current. In this thesis, several FID structures are fabricated and studied. First, two kinds of poly-Si TFT’s with a top sub-gate are fabricated and characterized. The devices feature a metal field-plate (sub-gate) lying over the passivation oxide and this field-plate is employed to induce an electrical junction in the channel offset region. From the results of device simulation, it is observed that the maximum electric field of the FID device is much smaller than that with conventional structure. Moreover, the electron concentration of FID device is comparable to that of conventional one in the main-channel region. The experimental results show that high anomalous leakage observed in conventional self-aligned devices could be suppressed using the FID approach. The characteristics of devices receiving different plasma treatment (NH3 and H2) are also explored and compared. Next, a novel thin film transistor with a self-aligned field-induced-drain (SAFID) structure is reported. In this new structure, a bottom sub-gate scheme along with a self-aligned field-induced drain (SAFID) defined by sidewall spacers were utilized. Superior device performance is realized with such strycture. Devices feature another top sub-gates architectures were also fabricated and characterized. The top sub-gate scheme allows the self-aligned formation of main-gate with respect to the sub-gate. However, the high resistive channel regions underneath the inner spacer will degrade the on-current performance. Besides, we investigated the effect of process temperature by fabricating devices with different passivation layers. Experimental and simulation results indicate temperature of passivation oxide deposition strongly impacts the device performance due to diffusion distance of dopants. High off-state leakage and poor ON/OFF current ratio would be resulted if the thermal budget is high. Conduction mechanisms and the effects of structural parameters on device performance of FID devices with bottom sub-gate were further investigated. The performance is significantly degraded by a drastic increase of off-state leakage current when the channel length is scaled below 1 □m. Moreover, a hump in subthreshold current-voltage regime is observed. Leakage path and possible cause for the leakage are identified based on the experimental results. . Finally, the effects of NH3 and H2 plasma passivation on the characteristics of aforementioned poly-Si thin-film transistors with source/drain extensions induced by a bottom sub-gate were studied. Our results show that, although significant improvements in device performance can be obtained by either passivation methods, the NH3-plasma-treatment appears to be more effective in reducing the off-state leakage, subthreshold swing, and ON/OFF current ratio, as compared to H2 plasma passivation. Furthermore, NH3 plasma treatment is also found to be more effective in reducing the anomalous subthrehold hump phenomenon. Detailed analysis suggests that all these improvements can be explained by the more effective passivation of the traps distributed in both the front and back sides of the channel by NH3 plasma treatment. We introduced two leakage mechanisms to explain the puzzle of anomalous leakage current in short channel devices. The channel width dependence was also examined. The dada suggested that completed plasma passivation process was performed in narrow devices, so the leakage could be effectively suppressed. In addition, hump-free behaviors of devices without CMP strongly support our conclusion that some defects generated during CMP process have significant effects on device performance.