具比例式記憶或大鄰近層之細胞非線性網路設計與分析及其應用

Abstract

本論文的主旨在於闡述細胞非線性網路架構之分析與設計及其在聯想式記憶體及圖像辨識上之應用。論文中包含下列三個主要部分: (1) 以雙載子接面電晶體乘除法器架構之比例式記憶細胞非線性網路之分析與設計; (2)含自我回授之鍵值之新型細胞化非線性網路的設計; (3)大鄰近層細胞非線性網路通用機器之概念設計。 首先，本論文中提出並分析一個用來製作超大積體電路神經網路系統的新型緊密雙載子接面電晶體乘除法器之架構，在這個新型的四象限乘法及二象限除法電流模式電路中，利用互補式金氧半製程中的寄生PNP雙載子接面電晶體之射極電流與基極射極間電壓呈指數關係來實現乘除法器。該乘除法器之的架構同時能被用來產生比例式鍵值並將該鍵值與對應之其它神經元輸出相乘，因此，這個雙載子接面電晶體乘除法器具有小的晶片面積與架構密集的優點，同時這個雙載子接面電晶體乘除法器已經成功的被應用來實現類比式聯想記憶體。這個類比式聯想記憶體網路能夠儲存多套的圖案樣本，此外，還可將帶有雜訊之圖像樣本辨識並還原回原來所習得之樣本。我們以0.35微米互補式金氧半製程技術設計與製作了一個具有9x9細胞陣列大小的比例式記憶類比細胞非線性網路晶片，模擬與實驗已經成功地驗證了這個9x9細胞陣列大小的雙載子接面電晶體神經元架構之類比細胞非線性網路。 其次，根據這個雙載子接面電晶體乘除法器所架構之原始比例式記憶細胞非線性網路，我們提出並分析一個新型比例式記憶之細胞非線性網路架構。在這新型的比例式記憶細胞非線性網路中，模版A之自我回授鍵值及被導入。另外不同於原始比例式記憶細胞非線性網路將所有絕對鍵值的絕對值相加來當比例式鍵值的分母，新型之比例式記憶細胞非線性網路簡化為直接取最大絕對值來當分母。雖然兩者略有不同，但就觀察模擬的結果，新型比例式記憶細胞非線性網路依舊保有增強習得樣本特徵的能力。對於新型之比例式記憶細胞非線性網路，其模擬結果顯示可習得18x18樣本個數達98個。而在雜訊程度為0.3的狀況下，即使學習98個樣本，其辨識率仍可達86.9%。 最後，我們提出並分析另一個具有大鄰近層數不對稱模版的新型細胞非線性網路通用機器架構。在傳統的細胞非線性網路通用機器中，僅單一鄰近層的鍵值可以被實現。此乃因受限於二維的製程無法實現大鄰近層等複雜的鍵值。而利用非直接連接之神經鍵，我們可以實現相當於大鄰近層細胞非線性網路的功能而不需要再額外連接大鄰近層的鍵值。三個大鄰近層細胞神經網路在雜訊消除、聯接物偵測與箭頭幻覺等正確的功能已經由軟體模擬成功的驗證。 經由模擬與實驗的驗證，本論文所發展出的以雙載子接面電晶體乘除法器架構成之比例式記憶細胞非線性網路對於設計字元辨識系統之單一晶片系統具有極大的潛力，而大鄰近層細胞非線性網路之設計則簡化了大鄰近層連線的複雜度。未來將朝上述領域繼續研究；並把聯想記憶體之比例式記憶功能整合於細胞非線性網路通用機器此一類比平行影像處理系統中。

In this thesis the new analog cellular nonlinear(neural) network structure with ratio memory and the cellular nonlinear(neural) network universal machine are designed and analyzed. The main parts of this thesis include: (1) the analysis and design of the cellular nonlinear(neural) network with ratio memory structure and the applied to the implementation of the analog associative memory; (2) the design of new ratio memory cellular nonlinear(neural) networks structure with self-feedback weight of template A; (3) the conceptual design of the new Cellular Nonlinear(Neural) Network Universal Machine with programmable large-neighborhood asymmetric templates. Firstly, the new elements, called analog current mode four-quadrant multiplier and two quadrant divider, which is applied in the ratio memory cellular nonlinear(neural) network for the compact implementation of VLSI neural network is proposed and analyzed. In the new element structure, the parasitic PNP Bipolar Junction Transistor (BJT) in the CMOS process is used to implement the multiplication and division. It utilizes the exponential relationship between the emitter current and the base-emitter voltage of parasitic PNP Bipolar Junction Transistor (BJT). Using this relation, both multiplication and division can be realized in a simple BJT structure. The BJT-based multiplier-divider has the advantages of compact structure and small chip size. The BJT-based multiplier-divider has been successfully applied to the implementation of the analog associative memory. The analog associative memory can store many sets of exemplar patterns. Moreover, the input patterns can be recognized and recovered to the correct patterns. An experimental chip of the proposed neuron-bipolar junction transistor (□BJT) analog associative memory with the cell size of 9x9 has been designed and fabricated by using 0.35 µm single-poly quadric-metal (SPQM) n-well CMOS technology. The analog associative memory has been successfully verified through both simulation and measurement in the ratio memory cellular nonlinear(neural) network with the sizes of 9x9. With simple and compact structure and high integration capability, the proposed BJT-based multiplier-divider has a great potential in the VLSI implementation of neural network. Secondly, based on the basic ratio memory cellular nonlinear(neural) network for associative memory, a new ratio memory cellular nonlinear(neural) networks (RMCNN) structure called the SRMCNN are proposed and analyzed. In the new RMCNN, the self-feedback weight of template A is applied for enlarge the numbers of stored patterns. Except the above additional templates, the learning algorithm is also a little different from the original RMCNN. In the new RMCNN, the denominator of the ratio weight is simplified to be the maximum absolute value of the absolute weight instead of the sum of the absolute value of the absolute weights. Thus, the sum circuit can be eliminated. Though the learned weights of the new RMCNN is different from the original RMCNN, the software simulation results display that the new RMCNN still keep feature enhancement. Furthermore, the new RMCNN can recognize and recover more patterns than the original RMCNN. The new RMCNN can learn up to 98 patterns. In the case of noise variance level being 0.3, the recovery rates of the new RMCNN is still up to 86.9%. Finally, the new cellular nonlinear(neural) network universal machine (CNNUM) structure with asymmetric templates and large-neighborhood is proposed and analyzed. In conventional CNNUM, only the single-neighboring cells are connected to the cell. It is because that the 2D CMOS technology limits the implementation of large-neighboring or complicated interconnections. Indirect connection used in the LN-CNN makes it being possible to implement the large-neighborhood templates without extra direct large-neighboring interconnections. As the demonstrative examples on the applications of the proposed large-neighborhood CNN, three functions of noise removal, connected component detection, and Muller-Lyer arrowhead illusion have been successfully realized and verified by software simulation with the corresponding templates. From the above results, it is believed that the proposed RMCNN structure and its application on pattern recognition have a great potential in system-on-a-chip design of the neural network systems, and the proposed LN-CNNUM structure can simplify the complex of the large-neighborhood interconnections. Further researches in the two fields will be conducted in the future, and the ratio memory structure will be embedded into the analog parallel image processor.