場效電晶體高頻模型的建立及矽鍺合金層應用於高介電物質電晶體對電洞遷移率的改善

Abstract

互補式金氧半場效電晶體具有價格便宜、整合性高的優點，因此在一些需要較低功率的射頻電路中，有極高的潛力取代高價的三五族製程。對於電路設計者來說，正確的場效電晶體高頻模型對於電路是十分地重要的。從我們建立的模型中，可以成功地預測閘極長度從0.18□m到0.13□m的射頻電晶體的S參數及雜訊特性，另外，我們也研究了不同元件佈局對於高頻電晶體相關特性的影響，並且發現在某個元件佈局時，可以達到最低的雜訊，這對於低雜訊放大器設計的元件選擇是重要的。在電晶體不斷地微縮時，我們必須使用高介電係數物質來降低元件關閉時的功率以及增加電晶體的電流驅動力，因為高介電係數的使用，將會降低通道電子電洞的載子遷移率。不過在高頻電晶體中，載子的遷移率對於電晶體的操作速度有極大的影響。我們使用了矽鍺非應力層的方法來提升電洞的遷移率。利用我們的方法，可以製作出不同鍺含量的單晶矽鍺非應力層，而且有很平整的表面。另外，從漏電流和電容電壓的曲線圖，以及可靠度測試的資料中，我們可以發現我們的高介電係數氧化層的品質十分良好。從汲極電流特性中，我們可以發現矽鍺的P型電晶體有兩倍於矽標準電晶體的驅動力，另外也可以將電洞的遷移率提高1.8倍，有效解決將高介電物質導入未來VLSI技術所遇到的瓶頸。

Because CMOS has advantages of low-cost and highly integrity, it has potential to replace the III-V device in low-power front-end circuit. In the respect of circuit designer, the accurate model is important for circuit performance. In our universal model, we can successfully predict the S-parameter and noise characteristic. In addition, we also study the layout dependent characteristic of RF MOSFET. The optimized finger numbers with optimized noise can be found in both 0.18μm and 0.13μm NMOSFET, which is essential for low noise amplifier designer. Besides, to continuously scale down the dimension of MOSFET, it is unavoidable of using high-□ dielectric to reduce gate leakage current and improve current drive capability. When applying high-□□dielectric, it also degrades the carrier mobility. The operation frequency of RF MOSFET is highly dependent on carrier mobility. We use novel strain-relaxed Si0.3Ge0.7 channel device to improve hole mobility. In our study, we have successfully fabricated single crystalline with different Ge content and smooth surface. As can be seen in leakage current density, C-V characteristic and reliability test of PMOSFET, we found the quality of high-□□and SixGe1-x layer is good. We can also improve the current drive capability and hole mobility to 2 times higher and 1.8 times higher than Si control device. We can efficiently overcome the problems when introducing high-□ dielectric into VLSI technology.