1-V 2.4-GHz互補式金氧半雙正交架構射頻前端接收器

Abstract

因應低電壓及低耗電為積體電路發展趨勢，本論文提出工作於1-V電源及2.4-GHz之互補式金氧半低雜訊放大器及雙正交射頻接收器，透過國家晶片系統設計中心，以臺灣積體電路製造股份有限公司提供的 .25-mm製程技術實現。其中雙正交射頻接收器所含電路有低雜訊放大器、正交產生器、正交壓控振盪器及降頻器。所提出的低雜訊放大器及雙正交射頻接收器皆成功地設計、製造及測試完成。 量測結果顯示，所設計的低雜訊放大器及雙正交射頻接收器可於1-V電源下正常運作。低雜訊放大器有著–19-dB輸入反射因數、17-dB增益及5.5-dB雜訊指數，線性度表現則達到–8-dBm三階輸入截點值；雙正交射頻接收器則有–20-dB輸入反射因數、12-dB增益、28-dB雜訊指數、30.2-dB鏡像拒斥比、–15-dB三階輸入截點值及–55-dBm內部振盪訊號漏溢。此外，該低雜訊放大器與接收器僅分別消耗4.0-mW及34.6-mW功率，適用於以電池供電的通訊器材及藍芽無線傳輸應用。

For trends of low voltage and low power in integrated-circuit development, this thesis proposes a CMOS low-noise amplifier and a CMOS double-quadrature RF receiver, operating at 1-V power supply and 2.4-GHz. The proposal is realized by .25-mm technology supported by Taiwan Semiconductor Manufacturing Company via Chip Implementation Center. The double-quadrature RF receiver comprises a low-noise amplifier, a quadrature generator, a quadrature voltage-controlled oscillator and a downconverter. Both the proposed low-noise amplifier and double-quadrature RF receiver are successfully designed, fabricated and tested. Measured results reveal that the designed low-noise amplifier and double-quadrature RF receiver can operate well at 1-V power supply. The low-noise amplifier performs –19-dB input reflection coefficient, 17-dB gain and 5.5-dB noise figure. The linearity performance achieves –8-dBm input third intercept point. The double-quadrature RF receiver performs –20-dB input reflection coefficient, 12-dB gain, 28-dB noise figure, 30.2-dB image rejection ratio, –15-dB input third intercept point and –55-dBm leakage of local-oscillation signal. Besides, the low-noise amplifier and receiver consume merely 4.0-mW and 34.6-mW power respectively, adequate for battery-based communication equipments and Bluetooth applications.