整合於超大型積體電路標準單元設計流程的低功率技術

Abstract

隨著VLSI技術的不斷進步，功率消耗逐漸變成一個亟需解決的問題。同時，由於降低工作電壓使得漏電流在CMOS奈米製程中漸漸宰制了總功率消耗，因此如何有效的控制功率消耗以及抑制漏電流(Leakage)現象成了在奈米製程中相當重要的課題。在這一篇論文之中提出了使用目前可應用的電子自動化(EDA)軟體分別實踐電壓分離(Voltage Separation)，基極偏壓(Body Bias)，和功率閘(Power Switch)三項低功率電路技術。藉由電子自動化軟體的協助，這些低功率技術可以有效地快速整合至標準單元設計流程(Cell-Based Design Flow)中。利用電壓分離，適合的電壓可以分配到對應的功能單元(Functional Unit)中，以避免提供過高的電壓導致過剩的功率浪費。基極偏壓利用偏壓電晶體(Transistor)中的基極(Body)以調整啟動電壓(Threshold Voltage)，因為漏電流多寡與啟動電壓呈指數反比關係，所以可藉由調整適合的啟動電壓值控制漏電流大小。功率閘主要是在電路與供應電壓源之間的串接一個電壓開關，當電路進入閒置時，功率閘將開啟以切斷於供應電壓源之間的連接，由一些文獻中得知功率閘對於漏電流可以達到有效的抑止。藉由將低電壓技術整合於實體設計流程(Physical Design Flow)，可以實現帶有低功率技術特徵的電路。因此，此篇論文提供了可利用標準胞元設計流程(Cell-Based Design Flow)實現低功率電路技術的機會。論文之中所有的驗證跟設計都是使用TSMC 0.18um製程技術在實體設計流程中實現。

As the scaling of VLSI process technology in this end of Moore’s Law era, power dissipation and design has become an important issue. At the same time, voltage scale down make leakage power gradually dominates the total power consumption in nano-scale CMOS technology. Therefore, how to control power consumption and diminish the leakage power is essential in nano-scale process. In this thesis, we implement three low power techniques, which are Voltage Separation, Body Bias and Power Switch, utilizing existent EDA tool. Using the benefit which is provided via EDA tool, these low power techniques can be integrated into cell-based design flow rapidly. By using Voltage Separation, each functional unit can be feed with appropriate voltage level and avoid the excess power consumption from over-supply voltage. Body Bias uses biasing the body terminal of transistor to adjust the threshold voltage. Because the magnitude of leakage current has a exponential relation with threshold voltage, reducing leakage current is possible by increase of threshold voltage of transistor. Power switch is connecting power supply source series with a transistor. When circuit is in idle mode, the power switch is disconnected from power supply source. A significant reduction on leakage current can be achieved via power switch. By embedding low power techniques into physical design flow. A design circuit with low power technique feature is available. Therefore, this thesis provides an opportunity to realize several low power techniques relied on Cell-Based method. All implementation and verification within this thesis is used TSMC 0.18-un technology in physical design flow.