100MHz 10位元導管式類比數位轉換器之設計

Abstract

本論文研究 3V 100MHz 導管式類比數位轉換器(ADC)以TSMC 035um 製程參數之設計模擬。本論文中ADC架構是採用每一級1.5bit共八級和最後一級2bit，此ADC電路包含CMOS全差動取樣保持電路(S/H)，主要應用在高速轉換器的前端。我們利用拔靴帶電路(bootstrapping circuit)以降低電荷注入效應(signal dependent charge injection)，並且利用1.5bit寬共模範圍的數位類比轉換器以減少雜訊(noise)和功率消耗(power consunption)。在 3V電源供應(power supply)100MHz 周期頻率下本轉換器共消耗 269mW。微分和積分非線性誤差(Differential and Integral Nonlinearity, DNL and INL)在MATLAB的模擬下分別為0.73LSB和 LSB。

This thesis describes the design of a 3 V, 100MHz pipeline analog to digital converter (ADC) implemented by simulation with 0.35μm one-poly four-metal process. The ADC consists of eight 1.5-bit stages and the final stage is a 2-bit stage. It consists of CMOS full differential Sample and Hold circuit(S/H), which is mainly intended for front-end use in high speed ADC. Bootstrapping circuit is needed to reduce signal-dependent charge injection, and 1.5bit digital to analog converter (DAC) with wide common mode compliance reduce noise and power consumption. The A/D converter dissipates 269mW at a 100MHz clock rate with 3 V single supply voltage. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.73 LSB and LSB, respectively, by MATLAB simulation.