DSP全數位控制半橋式升壓型功率因數修正器之研製

Abstract

本論文研製以數位訊號處理器(DSP)為基礎之全數位控制半橋式交-直流轉換器，發展出一種具有多項控制特色的全數位式功率因數控制方法，解決一般電源供應器功率因數低落、諧波失真大及電磁干擾等問題。本文選擇普遍應用於中、高功率在線式不斷電系統(UPS)，符合配線法規之共水式半橋式升壓型功率因數修正電路架構，針對功率因數修正控制原理，探討功率因數修正電路之電路特性、脈寬調變控制方式、與動態特性。控制架構採用多迴路控制方式，包含電流內迴路、電壓外迴路、與均方根電壓補償迴路，同時配合電流修飾(current shaping)、輸出漣波電壓估測(output voltage ripple estimation)及不平衡控制(imbalance control)等方法，消除輸出兩倍線電壓漣波120Hz之電壓迴路頻寬限制，並且降低輸入電流失真及諧波大小，達到高頻寬快速響應之系統要求。本文提出之控制方法，具有簡單易於實現的優點，相對於傳統式類比控制，在穩態響應、非線性非平衡負載控制及暫態響應上，皆有顯著的改善。本文採用PSIM軟體進行半橋式交直流轉換器之數位式多迴路控制模擬，採用單晶片DSP (TMS320LF2407)數位控制器實現所提出之控制法則，並以一個1kVA的功率級完成系統整合之測試驗證。模擬與實驗結果顯示，本文所提出控制方法之效果及優越性，在全載輸出時，功率因數可達0.99，輸出電壓之全載步階響應回復時間約為50msec，理論與分析亦得到驗證。

This thesis presents the design and implementation of a DSP-based fully digital-controlled half-bridge boost power factor corrector (PFC). The common-neutral half-bridge boost PFC has an advantage of sharing a common neutral with input utility and output half-bridge PWM inverter and is generally adopted in middle-high power range uninterruptible power supply (UPS). The operational principle and control schemes of the half-bridge PFC converters are described and reviewed. This thesis proposes a multi-loop control scheme for the fast response control of the half-bridge PFC converter. The proposed controller consists of an inner current-loop controller, an outer voltage-loop controller, and a RMS voltage-loop controller. In order to improve the PFC control performance, we also develop auxiliary control schemes such as current shaping control, output voltage ripple estimation, imbalance control, and frequency-phase locked loop control. By using the voltage ripple estimator, the output voltage ripples can be eliminated from the feedback measurement and therefore the frequency bandwidth limit due to the 120Hz line voltage ripple has been removed. The input current distortion and harmonic components are also significantly reduced. The proposed control algorithm, which is simple and fast, provides a significant improvement in system dynamic responses of imbalance or nonlinear load compared to conventional analog control techniques. The proposed control scheme has been verified by using computer simulation with PSIM and implemented using a single-chip DSP (TMS320LF2407) controller. Experimental verification has been carried out on a 1 kVA half-bridge boost PFC converter. Experimental results show a power factor of 0.99 at rated output condition. The recovery time is about 50 msec for a rated step load change. Both of simulation and experimental results show the feasibility and superiority of the proposed digital PFC control scheme.