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dc.contributor.authorKer, Ming-Douen_US
dc.contributor.authorLin, Chun-Yuen_US
dc.date.accessioned2014-12-08T15:09:20Z-
dc.date.available2014-12-08T15:09:20Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0780-4en_US
dc.identifier.issn1071-9032en_US
dc.identifier.urihttp://hdl.handle.net/11536/7124-
dc.identifier.urihttp://dx.doi.org/10.1109/ICMTS.2007.374482en_US
dc.description.abstractWith the highest ESD level in a smallest layout area, SCR device was used as effective on-chip ESD protection device in CMOS technology. In this paper, a waffle layout test structure of SCR is proposed to investigate the current spreading efficiency for ESD protection. The SCR in waffle layout structure has smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to on-chip ESD protection device can be reduced. The proposed waffle SCR is suitable for on-chip ESD protection in RF applications.en_US
dc.language.isoen_USen_US
dc.titleTest structure on SCR device in waffle layout for RE ESD protectionen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/ICMTS.2007.374482en_US
dc.identifier.journal2007 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, PROCEEDINGSen_US
dc.citation.spage196en_US
dc.citation.epage199en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000247663800038-
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