使用週期性重置積分之低成本角度解調變晶片設計

Abstract

光學量測技術的非接觸性、非導電性、靈敏度和穩定性等等優勢，較一般使用電訊號為基礎的感測器擁有更多優點，因而被大量用於感測器應用上。其中光纖感測器具有多工量測能力以及體積小、質量輕、優異的環境適應性且架設容易等多項優點。而光纖量測訊號多為低頻及微弱的訊號，一般皆使用角度調變技術的方式將量測訊號帶離雜訊區，使之能正確的被解析出來。 本論文提出了一創新的角度解調變技術，解決了傳統角度解調變器對調變深度參數的嚴格要求，大幅提升前端光學系統的設計彈性，以及後端訊號處理的即時性與可靠度。相較於一般的解調變器，使用本論文所提出之角度解調變理論所實現之解調變器電路不需使用面積大且成本高昂的電路元件，可以有效降低解調變電路之面積與成本。 為驗證所提出之理論，我們採用TSMC 0.18μm 1P6M CMOS製程設計了一顆測試晶片並送交CIC製作完成。電路實現上採用全差動切換電容式架構，不僅解決了傳統解調變器電路設計上最難克服的線性度問題，同時大幅降低所使用的電容值，使整體電路能夠積體電路化，達到體積小、速度快、靈敏度高、可靠度高、環境適應性強等特性。整體測試晶片面積為958×826μm^2，核心電路面積僅佔476×368μm^2。相較於使用離散元件實現的電路，縮小面積達160,000倍、降低功率消耗達5000倍以上。解調變範圍最高可處理載波頻率128kHz的信號，功率消耗為17.26mW。

Optical measurement systems have the advantages of being non-contact, non-conductive, with high sensitivity, stabile and so on. It can be used extensively for sensor applications, and have more advantages than electronic based sensors. Fiber Optic Sensor has a multiplex measurement capability and lots of advantages, such as small size, light weight, excellent environmental adaptability and easy to set up. The measurement signal of fiber sensor is mostly low frequency and weak signal; need to use the angle modulation techniques to take the measurement signal away from the noise floor. The modulation technique is helpful because the analog signal process make the measurement signal more correctly to be resolved. This thesis proposes a periodically resetting integration (PRI) method for implementing cost-effective angle demodulator. Contrary to conventional designs with discrete components, the proposed angle demodulator does not need complicated and high precision analog building blocks, such as bulky band-pass filters, linear analog multipliers, and lock-in amplifiers. In particular, the proposed PRI technique also allows a wide range of the modulation depth. As a consequence, it greatly alleviates design efforts and costs of the angle modulated optical measurement systems. A test chip containing the proposed PRI angle demodulator, an instrumentation amplifier and an output buffer has been designed and fabricated in TSMC 0.18μm 1P6M CMOS technology through the services of the Chip Implementation Center (CIC), Taiwan. The design uses a fully-differential switched-capacitor (SC) architecture which provides good linearity and well suits for IC implementations. The total test chip area occupies 958 × 826 μm^2, with the angle demodulator core taking up only 476 × 368 μm^2. It achieves an area reduction factor of 160,000. Measurement results show that the demodulator can accommodate a carrier frequency up to 128 kHz. The measured peak signal-to-noise-ratio (SNR) and Signal-to-noise plus distortion ratio (SNDR) are 49.77dB and 49.10dB, respectively. It consumes 17.26mW from a 1.8V supply. The power reduction factor is over 5,000. The proposed PRI demodulator design achieves a small area, low power, a high speed, less sensitive to the modulation depth, and high reliability.