高壓金氧半場效電晶體臨界電壓飄移構因研究

Abstract

進入二十一世紀後，各式3C用品的需求與日俱增，從而帶動了大量各式尺寸面板的需求，高壓金氧半場效電晶體製程目前大宗應用於LCD驅動IC，並使用在各式液晶電視、手機與平板電腦。 由於高壓製程臨界電壓的穩定度直接影響驅動IC的品質與應用，而其中又以PMOS臨界電壓更容易飄移，由WAT(Wafer Acceptance Test)的測試結果，發現共有兩種飄移型態，一種為高P低N臨界電壓飄移，另一種為高N低P臨界電壓飄移。本文主要是針對高壓製程臨界電壓飄移之構因探討，並提出解決方案。 研究方法主要是利用各種故障分析工具分析臨界電壓飄移元件，再由高壓製程各參數實驗之WAT分析結果比較得知，高壓元件臨界電壓的故障原因，是Cap oxide太薄，而由大量數據結果發現若是爐管的特定相關高壓製程之參數非最佳化，爐管內晶圓擺放位置會影響Cap oxide的厚度而導致臨界電壓飄移。最後，經由實驗分析後修正相關高壓爐管製程參數後，高壓元件臨界電壓便不會隨著爐管晶圓擺放位置而飄移。

The rapid increase in the demand of 3C consumer products requires a fast supply of a large quantity of flat panel displays of different dimensions. Nowadays, the liquid crystal display (LCD) is the standard display panel for various kinds of television sets, mobile phones and tablet computers. These LCD displays are controlled by integrated circuit (IC) drivers that are fabricated using the high-voltage (HV) metal-oxide-semiconductor (MOS) field-effect transistor (FET) process. The stability of the threshold voltage (VT) of HV-MOSFET drivers greatly affect the performance of the LCD panel displays. From the wafer acceptance test (WAT), two types of VT instability (or drift) are found to occur to the HV-MOSFET drivers. One type is a high VT in the P-type MOS (PMOS) but a low VT in the N-type MOS (NMOS); the other is a high VT in NMOS but a low VT in PMOS. In the thesis, we study the failure cause of the VT drift of the HV-MOSFET drivers. We used WAT analysis, in conjunction with various material analysis techniques, to study the dependence of the VT drift on the parameters of the fabrication processes of the HV-MOSFET drivers. From the study, we found that a thin initial oxide layer before the ion implantation (IMP) will result in a serious VT drift. The formation of the thin oxide layer may occur due to following improper process conditions: the time of IMP drive-in, the time for the pre-IMP wet clean, and the waiting time between the pre-IMP wet-clean and the IMP process.This study found that the main factor causing the VT drift of the HV-MOSFET driver was the wafer location in the furnace for the deposition of the sacrificial oxide and the pad oxide for the shallow trench isolation process. The placement of wafers on the top section of the furnace may result in an opposite VT drift to that on the bottom section. This is due to the non-uniform distribution of the oxygen flow in the furnace. The problem of the VT drift of the HV-MOSFET drivers was eliminated by the modification of the furnace deposition conditions of the pad oxide in the shallow trench isolation process.