控制氧空缺或氧離子分佈於過渡金屬氧化物薄膜之電阻式記憶體元件的影響

Abstract

快閃記憶體由於其高密度與低製作成本因素，是現今非揮發性記憶體的主流。然而它有許多缺點，包含：較差的耐久力、慢的操作速度與高的操作電壓。而且，隨著電子元件不斷微縮，快閃記憶體將遇到物理微縮極限，導致快閃記憶體之資料保存能力。此外，電阻式記憶體因其在超高密度積體化下，擁有高操作速度、長記憶時間、高操作次數、非破壞性讀取能力、低功率操作、低操作電壓、簡單結構、高微縮能力與可多位元儲存能力等優點，因此被高度注目以期待成為下世代非揮發性記憶體元件。 本論文實驗分為兩部分，第一部分以原子層沉積系統沉積氮化鈦為底電極，搭配以射頻磁控濺鍍法沉積的氧化鋯為電阻轉態層，以射頻磁控濺鍍法沉積的鋯為上電極，以鎢當作覆蓋層，形成一覆蓋層/上電極/電阻轉態層/下電極的結構。我們探討不同厚度的鋯上電極對於元件電阻轉態特性的影響，實驗結果顯示，不同的鋯厚度能改變電阻轉換的操作極性，以及能增加元件的耐久度和良率。另一方面，在很薄的氧化鋯薄膜厚度下，改變不同上電極鋯厚度亦對元件轉態特性有影響，。最後發現在此條件下的元件，展現出低操作電流 (<1毫安培)、低操作電壓(寫入/抹除,0.6/-1 伏特)、高直流操作次數(16000次)、高動態操作次數(10^7次)、快速的元件轉態速度(40 ns)、與所儲存記憶狀態於攝氏125度之下可被儲存104秒之特性。 第二部分以原子層沉積系統沉積氮化鈦為底電極，之後以原子層沉積系統沉積沉積氧化鉿當作轉換電阻層，上電極鈦和覆蓋層白金則利用電子束蒸鍍法製備，形成一覆蓋層/上電極/電阻層/下電極的結構。此外，由於電阻轉態過程會消耗掉氧離子導致元件耐久度衰弱，利用氧電漿處理後的氧化鉿，能產生額外的氧離子且有效增加元件耐久度，為避免上電極鈦直接抓取氧化鉿上的額外氧離子(無助於改善特性)，我們沉積了一層薄的氧化鉿薄膜以分開上電極鈦和氧電漿處理後的氧化鉿直接接觸，在此結構中的元件耐久度衰弱能被改善，並且，此結構具有快速的轉態速度和高轉換次數，因此此結構有機會成為下世代非揮發式記憶體的主流。

Flash memory device is the most prominent NVM owing to its high density and low fabrication costs. However, Flash memory reveals low endurance, slow operation speed, and high voltage. Moreover, the dimension as scaled toward 10 nm region, flash memory device will have serious challenges such as an unacceptable degradation of retention characteristic due to increasing difficulty of retaining electrons. Recently, RRAM has received great attention as the next generation nonvolatile memory device due to its advantages of fast operation speed, long retention time, high endurance, nondestructive readout, low power consumption, low operation voltage, simple constitution, high scalability, and multi-bit data storage capability for ultra-high density integration. The experiment of this thesis consists of two parts. The first part, we deposited a TiN as bottom electrode by atomic layer deposition (ALD). Next, the ZrO2 resistive switching layer and top electrode Zr films are deposited. The resistive switching layer of ZrO2 is deposited on the TiN bottom electrode by RF sputtering. In addition, the top electrode Zr is deposited on the ZrO2 by RF sputtering. Finally, A W capping layer is deposited by RF sputtering on the top electrode. Therefore, the TiN/ZrO2/Zr/W structure is fabricated. Furthermore, we discussed the influence of different thicknesses of Zr top electrode for resistive switching properties. The resistive switching properties, such as polarization, endurance and device yield, can be modified by different thickness of Zr top electrode. In addition, we told about special condition like different ultra-thin ZrO2 thickness, it can cause device polarization and performance modulation. Finally, the present device shows the low operate current(<1 mA), low operate voltage(program/erase,1.5/-1.2 V), high DC endurance cycles(16000 cycles), high dynamic endurance cycles(107 cycles), high switching speed(40 ns) and memory state can be stored in 125 oC for 104 s. Secondary, the TiN bottom electrode and HfO2 resistive switching layer are deposited by atomic layer deposition (ALD). Next, the Ti top electrode and Pt capping layer are deposited by E-beam evaporator to form the TiN/HfO2/Ti/Pt structure. Base on the mechanism of endurance degradation issue caused by no sufficient oxygen ions for resistive switching, we use oxygen plasma treatment in HfO2 layer to increase the extra available oxygen ions in RRAM devices. In addition, to avoid the Ti top electrode directly absorbs the additional oxygen from HfO2 layer with oxygen plasma treatment (no evident improvement of endurance properties), we insert the HfO2 thin film to separate them. Therefore, the endurance degradation issue can be suppressed in our device structure. High speed and large endurance cycles are achieved in this device structure for next generation nonvolatile memory application.