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dc.contributor.authorKer, Ming-Douen_US
dc.contributor.authorLiao, Hung-Taien_US
dc.date.accessioned2014-12-08T15:09:27Z-
dc.date.available2014-12-08T15:09:27Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0920-4en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/7223-
dc.identifier.urihttp://dx.doi.org/10.1109/ISCAS.2007.378207en_US
dc.description.abstractIn the nanometer-scale CMOS technology, the gate-oxide thickness has been scaled down to support a higher operating speed under a lower power supply (1xVDD). However, the board-level voltage levels could be still in a higher voltage levels (2xVDD, or even more) for compatible to some earlier interface specifications in a microelectronics system. The I/O interface circuits have been designed with consideration on the gate-oxide reliability in such mixed-voltage applications. In this work, a new mixed-voltage crystal oscillator circuit realized with low-vottage CMOS devices is proposed without suffering the gate-oxide reliability issue. The proposed mixed-voltage crystal oscillator circuit, which is one of the key I/O cells in a cell library, has been designed and verified in a 90-nm 1-V CMOS process to serve 1/1.8-V mixed-voltage interface applications.en_US
dc.language.isoen_USen_US
dc.titleDesign of mixed-voltage crystal oscillator circuit in low-voltage CMOS technologyen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/ISCAS.2007.378207en_US
dc.identifier.journal2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11en_US
dc.citation.spage1121en_US
dc.citation.epage1124en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000251608401098-
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