用低壓元件實現之混合電壓共容石英振盪電路設計

Abstract

隨著互補式金氧半（CMOS）製程技術進步至奈米尺寸（Nanometer-Scale），為了要在一個較低的供應電壓（1xVDD）下能提供更快的操作速度，閘極氧化層的厚度也必須跟著下降，然而在電路板上的電壓準位為了能相容於較早期的微電子系統介面規格，有可能還維持在較高的電壓準位（2xVDD或是更高），所以針對此種混合電壓共容應用的輸入輸出介面電路設計上，則要考量閘極氧化層可靠度（Gate-Oxide Reliability）、熱載子衰退效應（Hot-Carrier Degradation）以及漏電流（Leakage Current）等的問題。 在本篇論文中，提出了三種混合電壓介面電路，第一個電路是使用閘極電壓追隨電路（Gate-Tracking Circuit）以及動態N型井偏壓電路（Dynamic N-Well Bias Circuit）實現之混合電壓輸入輸出緩衝器（Mixed-Voltage I/O Buffer），目的是為了改善之前的混合電壓輸入輸出介面電路的一些問題，第二個電路是新提出的混合電壓石英振盪電路一，第三個電路是新提出的混合電壓石英振盪電路二，上述所提之三個電路皆以低壓元件實現之，且成功克服在混合電壓介面下的閘極氧化層可靠度問題。上述所提之三個混合電壓介面電路皆已在1.2伏0.13微米互補式金氧半製程裡實現，用以操作在1.2/2.5伏的混合電壓介面下；並且針對第二及第三個新提出的混合電壓石英振盪電路，又另外實現在1伏90奈米互補式金氧半製程中，用以操作在1/1.8伏的混合電壓介面。

In the nanometer-scale CMOS technology, the gate-oxide thickness has been scaled down to support a higher operating speed under a lower power supply (1xVDD). However, the board-level voltage levels could be still in a higher voltage levels (2xVDD, or even more) for compatible to some earlier interface specifications in a microelectronics system. The I/O interface circuits have been designed with considerations on the gate-oxide reliability, leakage current and hot-carrier degradation in such mixed-voltage applications. In this thesis, three kinds of mixed-voltage interface circuits are presented, The first is the mixed-voltage I/O buffer with gate-tracking circuit and dynamic n-well bias circuit for improving some drawbacks of the prior ones, the second is the new proposed mixed-voltage crystal oscillator circuit Ⅰ and the third is the new proposed mixed-voltage crystal oscillator circuit II. All of these three circuits have been realized with low-voltage CMOS devices to prevent the gate-oxide reliability issue and designed in a 130-nm 1.2-V CMOS process to serve 1.2/2.5-V mixed-voltage interface applications. Moreover, the new proposed mixed-voltage crystal oscillator circuit I and II have been also redesigned and realized in a 90-nm 1-V CMOS process to serve 1/1.8-V mixed-voltage interface applications.